Wenjie Jiang

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San Jose, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
Single stage pulsed domino circuit for driving cascaded skewed stat...
- Patent number 6,833,735
- Issue date Dec 21, 2004
- Intel Corporation
- Sudarshan Kumar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low power precharge scheme for memory bit lines
- Patent number 6,631,093
- Issue date Oct 7, 2003
- Intel Corporation
- Sudarshan Kumar
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for reducing soft errors in dynamic circuits
- Patent number 6,351,151
- Issue date Feb 26, 2002
- Intel Corporation
- Sudarshan Kumar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for reducing soft errors in dynamic circuits
- Patent number 6,292,029
- Issue date Sep 18, 2001
- Intel Corporation
- Sudarshan Kumar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low power multiplexer with shared, clocked transistor
- Patent number 6,111,435
- Issue date Aug 29, 2000
- Intel Corporation
- Jiann-Cherng James Lan
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
Single stage pulsed domino circuit for driving cascaded skewed stat...
- Publication number 20040124882
- Publication date Jul 1, 2004
- Intel Corporation
- Sudarshan Kumar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
LOW POWER PRECHARGE SCHEME FOR MEMORY BIT LINES
- Publication number 20030002382
- Publication date Jan 2, 2003
- Sudarshan Kumar
- G11 - INFORMATION STORAGE
Information Patent Application
Method and apparatus for reducing soft errors in dynamic circuits
- Publication number 20010040467
- Publication date Nov 15, 2001
- Sudarshan Kumar
- H03 - BASIC ELECTRONIC CIRCUITRY