Werner Juchmes

Person

Boeblingen, DE

People

Patents Grantslast 30 patents

Information Patent Grant
Digital logic circuit for deterring race violations at an array tes...
- Patent number 11,043,938
- Issue date Jun 22, 2021
- International Business Machines Corporation
- Harry Barowski
- G01 - MEASURING TESTING
Information Patent Grant
Digital logic circuit for deterring race violations at an array tes...
- Patent number 10,587,248
- Issue date Mar 10, 2020
- International Business Machines Corporation
- Harry Barowski
- G11 - INFORMATION STORAGE
Information Patent Grant
Digital logic circuit for deterring race violations at an array tes...
- Patent number 10,367,481
- Issue date Jul 30, 2019
- International Business Machines Corporation
- Harry Barowski
- G01 - MEASURING TESTING
Information Patent Grant
Content addressable memory array comprising geometric footprint and...
- Patent number 9,666,278
- Issue date May 30, 2017
- International Business Machines Corporation
- Alexander Fritsch
- G11 - INFORMATION STORAGE
Information Patent Grant
Hierarchical negative bitline boost write assist for SRAM memory de...
- Patent number 9,431,096
- Issue date Aug 30, 2016
- International Business Machines Corporation
- Alexander Fritsch
- G11 - INFORMATION STORAGE
Information Patent Grant
Reduced power consumption memory circuitry
- Patent number 8,422,313
- Issue date Apr 16, 2013
- International Business Machines Corporation
- Stefan Buettner
- G11 - INFORMATION STORAGE
Information Patent Grant
Test interface for memory elements
- Patent number 7,844,871
- Issue date Nov 30, 2010
- International Business Machines Corporation
- Uwe Brandt
- G11 - INFORMATION STORAGE
Information Patent Grant
Bypass circuit for memory arrays
- Patent number 7,558,138
- Issue date Jul 7, 2009
- International Business Machines Corporation
- Sebastian Ehrenreich
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
DIGITAL LOGIC CIRCUIT FOR DETERRING RACE VIOLATIONS AT AN ARRAY TES...
- Publication number 20200127649
- Publication date Apr 23, 2020
- International Business Machines Corporation
- Harry Barowski
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DIGITAL LOGIC CIRCUIT
- Publication number 20180212594
- Publication date Jul 26, 2018
- International Business Machines Corporation
- Harry Barowski
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DIGITAL LOGIC CIRCUIT
- Publication number 20180212595
- Publication date Jul 26, 2018
- International Business Machines Corporation
- Harry Barowski
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CONTENT ADDRESSABLE MEMORY ARRAY
- Publication number 20160099053
- Publication date Apr 7, 2016
- International Business Machines Corporation
- Alexander Fritsch
- G11 - INFORMATION STORAGE
Information Patent Application
REDUCED LEAKAGE BANKED WORDLINE HEADER
- Publication number 20130128684
- Publication date May 23, 2013
- International Business Machines Corporation
- Stefan Buettner
- G11 - INFORMATION STORAGE
Information Patent Application
REDUCED POWER CONSUMPTION MEMORY CIRCUITRY
- Publication number 20120155188
- Publication date Jun 21, 2012
- International Business Machines Corporation
- Stefan Buettner
- G11 - INFORMATION STORAGE
Information Patent Application
TEST INTERFACE FOR MEMORY ELEMENTS
- Publication number 20100122128
- Publication date May 13, 2010
- International Business Machines Corporation
- Uwe Brandt
- G11 - INFORMATION STORAGE

Werner Juchmes

Person

Patents Grantslast 30 patents

Digital logic circuit for deterring race violations at an array tes...

Digital logic circuit for deterring race violations at an array tes...

Digital logic circuit for deterring race violations at an array tes...

Content addressable memory array comprising geometric footprint and...

Hierarchical negative bitline boost write assist for SRAM memory de...

Reduced power consumption memory circuitry

Test interface for memory elements

Bypass circuit for memory arrays

Patents Applicationslast 30 patents

DIGITAL LOGIC CIRCUIT FOR DETERRING RACE VIOLATIONS AT AN ARRAY TES...

DIGITAL LOGIC CIRCUIT

DIGITAL LOGIC CIRCUIT

CONTENT ADDRESSABLE MEMORY ARRAY

REDUCED LEAKAGE BANKED WORDLINE HEADER

REDUCED POWER CONSUMPTION MEMORY CIRCUITRY

TEST INTERFACE FOR MEMORY ELEMENTS