William A. Shelly

Person

Phoenix, AZ, US

People

Patents Grantslast 30 patents

Information Patent Grant
Equal access to prevent gateword dominance in a multiprocessor writ...
- Patent number 6,970,977
- Issue date Nov 29, 2005
- Bull HN Information Systems Inc.
- Wayne R. Buzby
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High integrity cache directory
- Patent number 6,898,738
- Issue date May 24, 2005
- Bull HN Information Systems Inc.
- Charles P. Ryan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computer processor read/alter/rewrite optimization cache invalidate...
- Patent number 6,754,859
- Issue date Jun 22, 2004
- Bull HN Information Systems Inc.
- Bruce E. Hayden
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data processing system processor dynamic selection of internal sign...
- Patent number 6,530,076
- Issue date Mar 4, 2003
- Bull HN Information Systems Inc.
- Charles P. Ryan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Gate close balking for fair gating in a nonuniform memory architect...
- Patent number 6,484,272
- Issue date Nov 19, 2002
- Bull HN Information Systems, Inc.
- David A. Egolf
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Gate close failure notification for fair gating in a nonuniform mem...
- Patent number 6,480,973
- Issue date Nov 12, 2002
- Bull Information Systems Inc.
- William A. Shelly
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data processing system utilizing multiple resister loading for fast...
- Patent number 6,351,807
- Issue date Feb 26, 2002
- Bull HN Information Systems Inc.
- Ron W. Yoder
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for exhaustively testing interactions among mu...
- Patent number 6,249,880
- Issue date Jun 19, 2001
- Bull HN Information Systems Inc.
- William A. Shelly
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data processing system processor delay instruction
- Patent number 6,230,263
- Issue date May 8, 2001
- Charles P. Ryan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus for synchronizing multiple processors in a data processin...
- Patent number 6,223,228
- Issue date Apr 24, 2001
- Bull HN Information Systems Inc.
- Charles P. Ryan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Calendar clock caching in a multiprocessor data processing system
- Patent number 6,052,700
- Issue date Apr 18, 2000
- Bull HN Information Systems Inc.
- Clinton B. Eckard
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Information block transfer management in a multiprocessor computer...
- Patent number 6,006,309
- Issue date Dec 21, 1999
- Bull HN Information Systems Inc.
- William A. Shelly
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiprocessor computer system incorporating method and apparatus f...
- Patent number 5,963,973
- Issue date Oct 5, 1999
- Bull HN Information Systems Inc.
- Elisabeth Vanhove
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Private cache miss and access management in a multiprocessor system...
- Patent number 5,829,029
- Issue date Oct 27, 1998
- Bull HN Information Systems Inc.
- William A. Shelly
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fault tolerant multiprocessor computer system
- Patent number 5,649,090
- Issue date Jul 15, 1997
- Bull HN Information Systems Inc.
- David S. Edwards
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Basic operations synchronization and local mode controller in a VLS...
- Patent number 5,644,761
- Issue date Jul 1, 1997
- Bull HN Information Systems Inc.
- Ronald W. Yoder
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Central processor with duplicate basic processing units employing m...
- Patent number 5,515,529
- Issue date May 7, 1996
- William A. Shelly
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Central processor with duplicate basic processing units employing m...
- Patent number 5,495,579
- Issue date Feb 27, 1996
- Bull HN Information Systems Inc.
- William A. Shelly
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Safestore frame implementation in a central processor
- Patent number 5,276,862
- Issue date Jan 4, 1994
- Bull HN Information Systems Inc.
- Lowell D. McCulley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Error detection in the basic processing unit of a VLSI central proc...
- Patent number 5,263,034
- Issue date Nov 16, 1993
- Bull Information Systems Inc.
- Russell W. Guenthner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Binary to binary coded decimal and binary coded decimal to binary c...
- Patent number 5,251,321
- Issue date Oct 5, 1993
- Bull HN Information Systems Inc.
- Donald C. Boothroyd
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Distributor of machine words between units of a central processor
- Patent number 4,858,176
- Issue date Aug 15, 1989
- Honeywell Bull Inc.
- John E. Wilhite
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dual validity bit arrays
- Patent number 4,602,368
- Issue date Jul 22, 1986
- Honeywell Information Systems Inc.
- Joseph C. Circello
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for prefetching instructions for a central exe...
- Patent number 4,594,659
- Issue date Jun 10, 1986
- Honeywell Information Systems Inc.
- Russell W. Guenthner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Central processor
- Patent number 4,521,851
- Issue date Jun 4, 1985
- Honeywell Information Systems Inc.
- Leonard G. Trubisky
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction buffer associated with a cache memory unit
- Patent number 4,521,850
- Issue date Jun 4, 1985
- Honeywell Information Systems Inc.
- John E. Wilhite
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for initiating the execution of instructions u...
- Patent number 4,471,432
- Issue date Sep 11, 1984
- John E. Wilhite
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data processing system programmable pre-read capability
- Patent number 4,371,927
- Issue date Feb 1, 1983
- Honeywell Information Systems Inc.
- John E. Wilhite
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache arrangement utilizing a split cycle mode of operation
- Patent number 4,245,304
- Issue date Jan 13, 1981
- Honeywell Information Systems Inc.
- Marion G. Porter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache unit with transit block buffer apparatus
- Patent number 4,217,640
- Issue date Aug 12, 1980
- Honeywell Information Systems Inc.
- Marion G. Porter
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Equal access to prevent gateword dominance in a multiprocessor writ...
- Publication number 20040193804
- Publication date Sep 30, 2004
- Bull HN Information Systems Inc.
- Wayne R. Buzby
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Computer processor read/alter/rewrite optimization cache invalidate...
- Publication number 20040111656
- Publication date Jun 10, 2004
- Bruce E. Hayden
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
High integrity cache directory
- Publication number 20030018936
- Publication date Jan 23, 2003
- Bull NH Information Systems Inc.
- Charles P. Ryan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Computer processor read/alter/rewrite optimization cache invalidate...
- Publication number 20020087925
- Publication date Jul 4, 2002
- Bull HN Information Systems Inc.
- Bruce E. Hayden
- G06 - COMPUTING CALCULATING COUNTING

William A. Shelly

Person

Patents Grantslast 30 patents

Equal access to prevent gateword dominance in a multiprocessor writ...

High integrity cache directory

Computer processor read/alter/rewrite optimization cache invalidate...

Data processing system processor dynamic selection of internal sign...

Gate close balking for fair gating in a nonuniform memory architect...

Gate close failure notification for fair gating in a nonuniform mem...

Data processing system utilizing multiple resister loading for fast...

Method and apparatus for exhaustively testing interactions among mu...

Data processing system processor delay instruction

Apparatus for synchronizing multiple processors in a data processin...

Calendar clock caching in a multiprocessor data processing system

Information block transfer management in a multiprocessor computer...

Multiprocessor computer system incorporating method and apparatus f...

Private cache miss and access management in a multiprocessor system...

Fault tolerant multiprocessor computer system

Basic operations synchronization and local mode controller in a VLS...

Central processor with duplicate basic processing units employing m...

Central processor with duplicate basic processing units employing m...

Safestore frame implementation in a central processor

Error detection in the basic processing unit of a VLSI central proc...

Binary to binary coded decimal and binary coded decimal to binary c...

Distributor of machine words between units of a central processor

Dual validity bit arrays

Method and apparatus for prefetching instructions for a central exe...

Central processor

Instruction buffer associated with a cache memory unit

Method and apparatus for initiating the execution of instructions u...

Data processing system programmable pre-read capability

Cache arrangement utilizing a split cycle mode of operation

Cache unit with transit block buffer apparatus

Patents Applicationslast 30 patents

Equal access to prevent gateword dominance in a multiprocessor writ...

Computer processor read/alter/rewrite optimization cache invalidate...

High integrity cache directory

Computer processor read/alter/rewrite optimization cache invalidate...