William B. Sadler

Person

Folsom, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Scalar core integration
- Patent number 12,117,962
- Issue date Oct 15, 2024
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic memory reconfiguration
- Patent number 11,954,062
- Issue date Apr 9, 2024
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data prefetching for graphics data processing
- Patent number 11,892,950
- Issue date Feb 6, 2024
- Intel Corporation
- Vikranth Vemulapalli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scalar core integration
- Patent number 11,762,804
- Issue date Sep 19, 2023
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Thread group scheduling for graphics processing
- Patent number 11,709,714
- Issue date Jul 25, 2023
- Intel Corporation
- Ben Ashbaugh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sparse optimizations for a matrix accelerator architecture
- Patent number 11,676,239
- Issue date Jun 13, 2023
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Preemptive page fault handling
- Patent number 11,416,411
- Issue date Aug 16, 2022
- Intel Corporation
- Murali Ramadoss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scalar core integration
- Patent number 11,409,693
- Issue date Aug 9, 2022
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data prefetching for graphics data processing
- Patent number 11,409,658
- Issue date Aug 9, 2022
- Intel Corporation
- Vikranth Vemulapalli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Thread group scheduling for graphics processing
- Patent number 11,281,496
- Issue date Mar 22, 2022
- Intel Corporation
- Ben Ashbaugh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sparse optimizations for a matrix accelerator architecture
- Patent number 11,113,784
- Issue date Sep 7, 2021
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scalar core integration
- Patent number 11,016,929
- Issue date May 25, 2021
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data prefetching for graphics data processing
- Patent number 10,909,039
- Issue date Feb 2, 2021
- Intel Corporation
- Vikranth Vemulapalli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Rasterization based on partial spans
- Patent number 10,269,154
- Issue date Apr 23, 2019
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
SCALAR CORE INTEGRATION
- Publication number 20250068588
- Publication date Feb 27, 2025
- Intel Corporation
- JOYDEEP RAY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA PREFETCHING FOR GRAPHICS DATA PROCESSING
- Publication number 20240256456
- Publication date Aug 1, 2024
- Intel Corporation
- Vikranth Vemulapalli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC MEMORY RECONFIGURATION
- Publication number 20240184739
- Publication date Jun 6, 2024
- Intel Corporation
- Joydeep RAY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCALAR CORE INTEGRATION
- Publication number 20240045830
- Publication date Feb 8, 2024
- Intel Corporation
- JOYDEEP RAY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
THREAD GROUP SCHEDULING FOR GRAPHICS PROCESSING
- Publication number 20240028404
- Publication date Jan 25, 2024
- Intel Corporation
- Ben Ashbaugh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SPARSE OPTIMIZATIONS FOR A MATRIX ACCELERATOR ARCHITECTURE
- Publication number 20230351543
- Publication date Nov 2, 2023
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA PREFETCHING FOR GRAPHICS DATA PROCESSING
- Publication number 20230051190
- Publication date Feb 16, 2023
- Intel Corporation
- Vikranth Vemulapalli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCALAR CORE INTEGRATION
- Publication number 20230029176
- Publication date Jan 26, 2023
- Intel Corporation
- JOYDEEP RAY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
THREAD GROUP SCHEDULING FOR GRAPHICS PROCESSING
- Publication number 20220261289
- Publication date Aug 18, 2022
- Intel Corporation
- Ben Ashbaugh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC MEMORY RECONFIGURATION
- Publication number 20220066931
- Publication date Mar 3, 2022
- Intel Corporation
- JOYDEEP RAY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SPARSE OPTIMIZATIONS FOR A MATRIX ACCELERATOR ARCHITECTURE
- Publication number 20210374897
- Publication date Dec 2, 2021
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCALAR CORE INTEGRATION
- Publication number 20210349848
- Publication date Nov 11, 2021
- Intel Corporation
- JOYDEEP RAY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA PREFETCHING FOR GRAPHICS DATA PROCESSING
- Publication number 20210255957
- Publication date Aug 19, 2021
- Intel Corporation
- Vikranth Vemulapalli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SPARSE OPTIMIZATOINS FOR A MATRIX ACCELERATOR ARCHITECTURE
- Publication number 20210035258
- Publication date Feb 4, 2021
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRANSACTIONAL PAGE FAULT HANDLING
- Publication number 20200293365
- Publication date Sep 17, 2020
- Intel Corporation
- NIRAN COORAY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PREEMPTIVE PAGE FAULT HANDLING
- Publication number 20200293456
- Publication date Sep 17, 2020
- Intel Corporation
- MURALI RAMADOSS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
THREAD GROUP SCHEDULING FOR GRAPHICS PROCESSING
- Publication number 20200293380
- Publication date Sep 17, 2020
- Intel Corporation
- Ben Ashbaugh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCALAR CORE INTEGRATION
- Publication number 20200293488
- Publication date Sep 17, 2020
- Intel Corporation
- JOYDEEP RAY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA PREFETCHING FOR GRAPHICS DATA PROCESSING
- Publication number 20200293450
- Publication date Sep 17, 2020
- Intel Corporation
- Vikranth Vemulapalli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Rasterization Based on Partial Spans
- Publication number 20170178370
- Publication date Jun 22, 2017
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Dynamic selection of high-performance pixel shader code based on ch...
- Publication number 20080012874
- Publication date Jan 17, 2008
- Steven J. Spangler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and method for rasterization order independent line stipple
- Publication number 20070146366
- Publication date Jun 28, 2007
- Intel Corporation
- Avinash Seetharamaiah
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Variable-formatable width buffer and method of use
- Publication number 20030063087
- Publication date Apr 3, 2003
- Peter L. Doyle
- G06 - COMPUTING CALCULATING COUNTING

William B. Sadler

Person

Patents Grantslast 30 patents

Scalar core integration

Dynamic memory reconfiguration

Data prefetching for graphics data processing

Scalar core integration

Thread group scheduling for graphics processing

Sparse optimizations for a matrix accelerator architecture

Preemptive page fault handling

Scalar core integration

Data prefetching for graphics data processing

Thread group scheduling for graphics processing

Sparse optimizations for a matrix accelerator architecture

Scalar core integration

Data prefetching for graphics data processing

Rasterization based on partial spans

Patents Applicationslast 30 patents

SCALAR CORE INTEGRATION

DATA PREFETCHING FOR GRAPHICS DATA PROCESSING

DYNAMIC MEMORY RECONFIGURATION

SCALAR CORE INTEGRATION

THREAD GROUP SCHEDULING FOR GRAPHICS PROCESSING

SPARSE OPTIMIZATIONS FOR A MATRIX ACCELERATOR ARCHITECTURE

DATA PREFETCHING FOR GRAPHICS DATA PROCESSING

SCALAR CORE INTEGRATION

THREAD GROUP SCHEDULING FOR GRAPHICS PROCESSING

DYNAMIC MEMORY RECONFIGURATION

SPARSE OPTIMIZATIONS FOR A MATRIX ACCELERATOR ARCHITECTURE

SCALAR CORE INTEGRATION

DATA PREFETCHING FOR GRAPHICS DATA PROCESSING

SPARSE OPTIMIZATOINS FOR A MATRIX ACCELERATOR ARCHITECTURE

TRANSACTIONAL PAGE FAULT HANDLING

PREEMPTIVE PAGE FAULT HANDLING

THREAD GROUP SCHEDULING FOR GRAPHICS PROCESSING

SCALAR CORE INTEGRATION

DATA PREFETCHING FOR GRAPHICS DATA PROCESSING

Rasterization Based on Partial Spans

Dynamic selection of high-performance pixel shader code based on ch...

System and method for rasterization order independent line stipple

Variable-formatable width buffer and method of use