William B. Vest

Person

Santa Clara, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Integrated circuit decoupling capacitors
- Patent number 9,425,192
- Issue date Aug 23, 2016
- Altera Corporation
- Irfan Rahim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory elements with soft error upset immunity
- Patent number 9,412,436
- Issue date Aug 9, 2016
- Altera Corporation
- Irfan Rahim
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory elements with soft error upset immunity
- Patent number 8,797,790
- Issue date Aug 5, 2014
- Altera Corporation
- Irfan Rahim
- G11 - INFORMATION STORAGE
Information Patent Grant
Volatile memory elements with soft error upset immunity
- Patent number 8,289,755
- Issue date Oct 16, 2012
- Altera Corporation
- Irfan Rahim
- G11 - INFORMATION STORAGE
Information Patent Grant
Power regulator circuitry for programmable logic device memory elem...
- Patent number 8,085,063
- Issue date Dec 27, 2011
- Altera Corporation
- William Bradley Vest
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory elements with body bias control
- Patent number 8,081,502
- Issue date Dec 20, 2011
- Altera Corporation
- Irfan Rahim
- G11 - INFORMATION STORAGE
Information Patent Grant
Configuration random access memory
- Patent number 8,030,962
- Issue date Oct 4, 2011
- Altera Corporation
- Irfan Rahim
- G11 - INFORMATION STORAGE
Information Patent Grant
Process and temperature invariant power on reset circuit using a ba...
- Patent number 7,881,144
- Issue date Feb 1, 2011
- Altera Corporation
- Leo Min Maung
- G11 - INFORMATION STORAGE
Information Patent Grant
Power regulator circuitry for programmable logic device memory elem...
- Patent number 7,859,301
- Issue date Dec 28, 2010
- Altera Corporation
- William Bradley Vest
- G11 - INFORMATION STORAGE
Information Patent Grant
Configuration random access memory
- Patent number 7,800,400
- Issue date Sep 21, 2010
- Altera Corporation
- Irfan Rahim
- G11 - INFORMATION STORAGE
Information Patent Grant
Look-up table overdrive circuits
- Patent number 7,800,402
- Issue date Sep 21, 2010
- Altera Corporation
- Irfan Rahim
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Reducing power consumption by disabling power-on reset circuits aft...
- Patent number 7,786,770
- Issue date Aug 31, 2010
- Altera Corporation
- Gwen G. Liang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques for configuring programmable logic using on-chip nonvola...
- Patent number 7,710,147
- Issue date May 4, 2010
- Altera Corporation
- Thomas H. White
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Process and temperature invariant power on reset circuit using a ba...
- Patent number 7,391,665
- Issue date Jun 24, 2008
- Altera Corporation
- Leo Min Maung
- G11 - INFORMATION STORAGE
Information Patent Grant
Techniques for configuring programmable logic using on-chip nonvola...
- Patent number 7,375,551
- Issue date May 20, 2008
- Altera Corporation
- Thomas H. White
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated bus hold and pull-up resistor
- Patent number 7,154,296
- Issue date Dec 26, 2006
- Altera Corporation
- William B. Vest
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Routing architecture with high speed I/O bypass path
- Patent number 7,132,852
- Issue date Nov 7, 2006
- Altera Corporation
- William Bradley Vest
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Techniques for configuring programmable logic using on-chip nonvola...
- Patent number 7,030,647
- Issue date Apr 18, 2006
- Altera Corporation
- Thomas H. White
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable logic device having nonvolatile memory with user selec...
- Patent number 6,853,603
- Issue date Feb 8, 2005
- Altera Corporation
- Thomas H. White
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus of programmable interconnect array with config...
- Patent number 6,810,513
- Issue date Oct 26, 2004
- Altera Corporation
- William Bradley Vest
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cross coupled N-channel negative pump
- Patent number 6,664,846
- Issue date Dec 16, 2003
- Altera Corporation
- Min Maung
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
High voltage pump scheme incorporating an overlapping clock
- Patent number 6,236,260
- Issue date May 22, 2001
- Altera Corporation
- William B. Vest
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and circuit for reducing output ground and power bounce noise
- Patent number 6,184,703
- Issue date Feb 6, 2001
- Altera Corporation
- William B. Vest
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Power compensating voltage reference
- Patent number 6,005,379
- Issue date Dec 21, 1999
- Altera Corporation
- Myron W. Wong
- G05 - CONTROLLING REGULATING
Information Patent Grant
High voltage pump scheme incorporating an overlapping clock
- Patent number 5,793,246
- Issue date Aug 11, 1998
- Altera Corporation
- William B. Vest
- G11 - INFORMATION STORAGE
Information Patent Grant
High-voltage pump with initiation scheme
- Patent number 5,767,734
- Issue date Jun 16, 1998
- Altera Corporation
- William B. Vest
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
POWER REGULATOR CIRCUITRY FOR PROGRAMMABLE LOGIC DEVICE MEMORY ELEM...
- Publication number 20110062988
- Publication date Mar 17, 2011
- William Bradley Vest
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CONFIGURATION RANDOM ACCESS MEMORY
- Publication number 20100321984
- Publication date Dec 23, 2010
- Irfan Rahim
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
INTEGRATED CIRCUIT DECOUPLING CAPACITORS
- Publication number 20100148304
- Publication date Jun 17, 2010
- Irfan Rahim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Power regulator circuitry for programmable logic device memory elem...
- Publication number 20080265855
- Publication date Oct 30, 2008
- William Bradley Vest
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Configuration random access memory
- Publication number 20080169836
- Publication date Jul 17, 2008
- Irfan Rahim
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Routing architecture with high speed I/O bypass path
- Publication number 20050231236
- Publication date Oct 20, 2005
- Altera Corporation
- William Bradley Vest
- H03 - BASIC ELECTRONIC CIRCUITRY

William B. Vest

Person

Patents Grantslast 30 patents

Integrated circuit decoupling capacitors

Memory elements with soft error upset immunity

Memory elements with soft error upset immunity

Volatile memory elements with soft error upset immunity

Power regulator circuitry for programmable logic device memory elem...

Memory elements with body bias control

Configuration random access memory

Process and temperature invariant power on reset circuit using a ba...

Power regulator circuitry for programmable logic device memory elem...

Configuration random access memory

Look-up table overdrive circuits

Reducing power consumption by disabling power-on reset circuits aft...

Techniques for configuring programmable logic using on-chip nonvola...

Process and temperature invariant power on reset circuit using a ba...

Techniques for configuring programmable logic using on-chip nonvola...

Integrated bus hold and pull-up resistor

Routing architecture with high speed I/O bypass path

Techniques for configuring programmable logic using on-chip nonvola...

Programmable logic device having nonvolatile memory with user selec...

Method and apparatus of programmable interconnect array with config...

Cross coupled N-channel negative pump

High voltage pump scheme incorporating an overlapping clock

Method and circuit for reducing output ground and power bounce noise

Power compensating voltage reference

High voltage pump scheme incorporating an overlapping clock

High-voltage pump with initiation scheme

Patents Applicationslast 30 patents

POWER REGULATOR CIRCUITRY FOR PROGRAMMABLE LOGIC DEVICE MEMORY ELEM...

CONFIGURATION RANDOM ACCESS MEMORY

INTEGRATED CIRCUIT DECOUPLING CAPACITORS

Power regulator circuitry for programmable logic device memory elem...

Configuration random access memory

Routing architecture with high speed I/O bypass path