William Barth

Person

Gresham, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Dual damascene interconnect structure with improved electro migrati...
- Patent number 7,312,532
- Issue date Dec 25, 2007
- LSI Corporation
- Peter A. Burke
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Inter-layer interconnection structure for large electrical connections
- Patent number 7,160,805
- Issue date Jan 9, 2007
- LSI Logic Corporation
- Peter A. Burke
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual damascene interconnect structure with improved electro migrati...
- Patent number 7,033,929
- Issue date Apr 25, 2006
- LSI Logic Corporation
- Peter A. Burke
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for creating barrier layers for copper diffusion
- Patent number 6,998,343
- Issue date Feb 14, 2006
- LSI Logic Corporation
- Grace Sun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Layout design and process to form nanotube cell for nanotube memory...
- Patent number 6,969,651
- Issue date Nov 29, 2005
- LSI Logic Corporation
- Hongqiang Lu
- G11 - INFORMATION STORAGE
Information Patent Grant
PROCESS FOR REDUCING IMPURITY LEVELS, STRESS, AND RESISTIVITY, AND...
- Patent number 6,838,379
- Issue date Jan 4, 2005
- LSI Logic Corporation
- Byung-Sung Kwak
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Inter-layer interconnection structure for large electrical connections
- Patent number 6,642,597
- Issue date Nov 4, 2003
- LSI Logic Corporation
- Peter A. Burke
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Method for improved local planarity control during electropolishing
- Publication number 20050224358
- Publication date Oct 13, 2005
- LSI Logic Corporation
- Byung-Sung Kwak
- C25 - ELECTROLYTIC OR ELECTROPHORETIC PROCESSES APPARATUS THEREFOR
Information Patent Application
Dual damascene interconnect structure with improved electro migrati...
- Publication number 20050186782
- Publication date Aug 25, 2005
- LSI Logic Corporation
- Peter A. Burke
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of fabricating an alloy cap layer over CU wires to improve e...
- Publication number 20040207093
- Publication date Oct 21, 2004
- Sey-Shing Sun
- H01 - BASIC ELECTRIC ELEMENTS

William Barth

Person

Patents Grantslast 30 patents

Dual damascene interconnect structure with improved electro migrati...

Inter-layer interconnection structure for large electrical connections

Dual damascene interconnect structure with improved electro migrati...

Method for creating barrier layers for copper diffusion

Layout design and process to form nanotube cell for nanotube memory...

PROCESS FOR REDUCING IMPURITY LEVELS, STRESS, AND RESISTIVITY, AND...

Inter-layer interconnection structure for large electrical connections

Patents Applicationslast 30 patents

Method for improved local planarity control during electropolishing

Dual damascene interconnect structure with improved electro migrati...

Method of fabricating an alloy cap layer over CU wires to improve e...