William Burr Andrews

Person

Long Pound, PA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Pre-configuration programmability of I/O circuitry
- Patent number 8,384,428
- Issue date Feb 26, 2013
- Lattice Semiconductor Corporation
- William B. Andrews
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable buffer
- Patent number 8,324,934
- Issue date Dec 4, 2012
- Lattice Semiconductor Corporation
- Keith Truong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Flexible delay cell architecture
- Patent number 7,863,931
- Issue date Jan 4, 2011
- Lattice Semiconductor Corporation
- Fulong Zhang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Receiver for differential and reference voltage signaling with prog...
- Patent number 7,844,243
- Issue date Nov 30, 2010
- Lattice Semiconductor Corporation
- William B. Andrews
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Temperature-independent, linear on-chip termination resistance
- Patent number 7,714,608
- Issue date May 11, 2010
- Lattice Semiconductor Corporation
- Mou C. Lin
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Hysteresis-based processing for applications such as signal bias mo...
- Patent number 7,616,029
- Issue date Nov 10, 2009
- Lattice Semiconductor Corporation
- William B. Andrews
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable level shifter
- Patent number 7,605,609
- Issue date Oct 20, 2009
- Lattice Semiconductor Corporation
- William B. Andrews
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integrated circuit having independent voltage and process/temperatu...
- Patent number 7,586,325
- Issue date Sep 8, 2009
- Lattice Semiconductor Corporation
- William B. Andrews
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dynamic over-voltage protection scheme for interface circuitry
- Patent number 7,547,995
- Issue date Jun 16, 2009
- Lattice Semiconductor Corporation
- William B. Andrews
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Programmable current output and common-mode voltage buffer
- Patent number 7,535,258
- Issue date May 19, 2009
- Lattice Semiconductor Corporation
- Phillip L. Johnson
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Receiver for differential and reference-voltage signaling with prog...
- Patent number 7,505,752
- Issue date Mar 17, 2009
- Lattice Semiconductor Corporation
- William B. Andrews
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Temperature-independent, linear on-chip termination resistance
- Patent number 7,495,467
- Issue date Feb 24, 2009
- Lattice Semiconductor Corporation
- Mou C. Lin
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Output buffer with digital slew control
- Patent number 7,443,192
- Issue date Oct 28, 2008
- Lattice Semiconductor Corporation
- William B. Andrews
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable termination for single-ended and differential schemes
- Patent number 7,262,630
- Issue date Aug 28, 2007
- Lattice Semiconductor Corporation
- William B. Andrews
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Dynamic over-voltage protection scheme for integrated-circuit devices
- Patent number 7,230,810
- Issue date Jun 12, 2007
- Lattice Semiconductor Corporation
- William B. Andrews
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Programmable current output buffer
- Patent number 7,215,148
- Issue date May 8, 2007
- Lattice Semiconductor Corporation
- Phillip L. Johnson
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Interface circuitry for electrical systems
- Patent number 7,215,149
- Issue date May 8, 2007
- Lattice Semiconductor Corporation
- William B. Andrews
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Clock generation
- Patent number 7,091,763
- Issue date Aug 15, 2006
- Lattice Semiconductor Corporation
- Phillip Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adaptive input logic for phase adjustments
- Patent number 7,034,596
- Issue date Apr 25, 2006
- Lattice Semiconductor Corporation
- William B. Andrews
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Programmable I/O interfaces for FPGAs and other PLDs
- Patent number 7,009,423
- Issue date Mar 7, 2006
- Lattice Semiconductor Corporation
- William B. Andrews
- G11 - INFORMATION STORAGE
Information Patent Grant
Digitally controlled delay cells
- Patent number 7,009,433
- Issue date Mar 7, 2006
- Lattice Semiconductor Corporation
- Fulong Zhang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic devices with integrated standard-cell logic blocks
- Patent number 6,975,137
- Issue date Dec 13, 2005
- Lattice Semiconductor Corporation
- John A. Schadt
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable lock detector and corrector
- Patent number 6,970,047
- Issue date Nov 29, 2005
- Lattice Semiconductor Corporation
- Phillip Johnson
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Electronic circuit with on-chip programmable terminations
- Patent number 6,967,500
- Issue date Nov 22, 2005
- Lattice Semiconductor Corporation
- Mou C. Lin
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Programmable I/O interfaces for FPGAs and other PLDs
- Patent number 6,952,115
- Issue date Oct 4, 2005
- Lattice Semiconductor Corporation
- William B. Andrews
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable I/O structure for FPGAs and the like having reduced pa...
- Patent number 6,943,583
- Issue date Sep 13, 2005
- Lattice Semiconductor Corporation
- William B. Andrews
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable I/O structure for FPGAs and the like having shared cir...
- Patent number 6,943,582
- Issue date Sep 13, 2005
- Lattice Semiconductor Corporation
- William B. Andrews
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable signal termination for FPGAs and the like
- Patent number 6,924,659
- Issue date Aug 2, 2005
- Lattice Semiconductor Corporation
- William B. Andrews
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and apparatus for controlling signal distribution in an elec...
- Patent number 6,873,187
- Issue date Mar 29, 2005
- Lattice Semiconductor Corporation
- William Andrews
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable logic devices with integrated standard-cell logic blocks
- Patent number 6,870,395
- Issue date Mar 22, 2005
- Lattice Semiconductor Corporation
- John A. Schadt
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
Temperature-independent, linear on-chip termination resistance
- Publication number 20070164844
- Publication date Jul 19, 2007
- Mou C. Lin
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Digitally controlled delay cells
- Publication number 20040239387
- Publication date Dec 2, 2004
- Fulong Zhang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Programmable logic devices with integrated standard-cell logic blocks
- Publication number 20040183564
- Publication date Sep 23, 2004
- Lattice Semiconductor Corporation, a Delaware corporation
- John A. Schadt
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Adaptive input logic for phase adjustments
- Publication number 20040155690
- Publication date Aug 12, 2004
- Lattice Semiconductor Corporation
- William B. Andrews
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Signal distribution scheme in field programmable gate array (FPGA)...
- Publication number 20020003445
- Publication date Jan 10, 2002
- William B. Andrews
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multi-functional I/O buffers in a field programmable gate array (FPGA)
- Publication number 20020003435
- Publication date Jan 10, 2002
- William Burr Andrews
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Double data rate input and output in a programmable logic device
- Publication number 20020003436
- Publication date Jan 10, 2002
- William B. Andrews
- G06 - COMPUTING CALCULATING COUNTING

William Burr Andrews

Person

Patents Grantslast 30 patents

Pre-configuration programmability of I/O circuitry

Programmable buffer

Flexible delay cell architecture

Receiver for differential and reference voltage signaling with prog...

Temperature-independent, linear on-chip termination resistance

Hysteresis-based processing for applications such as signal bias mo...

Programmable level shifter

Integrated circuit having independent voltage and process/temperatu...

Dynamic over-voltage protection scheme for interface circuitry

Programmable current output and common-mode voltage buffer

Receiver for differential and reference-voltage signaling with prog...

Temperature-independent, linear on-chip termination resistance

Output buffer with digital slew control

Programmable termination for single-ended and differential schemes

Dynamic over-voltage protection scheme for integrated-circuit devices

Programmable current output buffer

Interface circuitry for electrical systems

Clock generation

Adaptive input logic for phase adjustments

Programmable I/O interfaces for FPGAs and other PLDs

Digitally controlled delay cells

Programmable logic devices with integrated standard-cell logic blocks

Programmable lock detector and corrector

Electronic circuit with on-chip programmable terminations

Programmable I/O interfaces for FPGAs and other PLDs

Programmable I/O structure for FPGAs and the like having reduced pa...

Programmable I/O structure for FPGAs and the like having shared cir...

Programmable signal termination for FPGAs and the like

Method and apparatus for controlling signal distribution in an elec...

Programmable logic devices with integrated standard-cell logic blocks

Patents Applicationslast 30 patents

Temperature-independent, linear on-chip termination resistance

Digitally controlled delay cells

Programmable logic devices with integrated standard-cell logic blocks

Adaptive input logic for phase adjustments

Signal distribution scheme in field programmable gate array (FPGA)...

Multi-functional I/O buffers in a field programmable gate array (FPGA)

Double data rate input and output in a programmable logic device