William C. Naylor

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Boolean satisfiability (SAT) solver
- Patent number 10,650,109
- Issue date May 12, 2020
- Synopsys, Inc.
- William Clark Naylor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Placement-based congestion-aware logic restructuring
- Patent number 10,346,578
- Issue date Jul 9, 2019
- Synopsys, Inc.
- Jagat B. Patel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Optimizing the ordering of the inputs to large commutative-associat...
- Patent number 10,331,834
- Issue date Jun 25, 2019
- Synopsys, Inc.
- Bogdan Craciun
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Detailed placer for optimizing high density cell placement in a lin...
- Patent number 8,069,429
- Issue date Nov 29, 2011
- Synopsys, Inc.
- Ronald Miller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Detailed placer for optimizing high density cell placement in a lin...
- Patent number 7,404,168
- Issue date Jul 22, 2008
- Synopsys, Inc.
- Ronald Miller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Detailed placer for optimizing high density cell placement in a lin...
- Patent number 7,036,103
- Issue date Apr 25, 2006
- Synopsys, Inc.
- Ronald Miller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Simultaneous placement of large and small cells in an electronic ci...
- Patent number 6,983,431
- Issue date Jan 3, 2006
- Synopsys, Inc.
- Ross A. Donelly
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Constrained optimization with linear constraints to remove overlap...
- Patent number 6,948,143
- Issue date Sep 20, 2005
- Synopsys, Inc.
- Ross A. Donelly
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple pass optimization for automatic electronic circuit placement
- Patent number 6,766,500
- Issue date Jul 20, 2004
- Synopsys, Inc.
- Ross A. Donelly
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Non-linear optimization system and method for wire length and delay...
- Patent number 6,671,859
- Issue date Dec 30, 2003
- Synopsys, Inc.
- William C. Naylor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Quick placement of electronic circuits using orthogonal one dimensi...
- Patent number 6,665,851
- Issue date Dec 16, 2003
- Synopsys, Inc.
- Ross A. Donelly
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Non-linear optimization system and method for wire length and densi...
- Patent number 6,662,348
- Issue date Dec 9, 2003
- Synopsys, Inc.
- William C. Naylor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Non-linear optimization system and method for wire length and delay...
- Patent number 6,301,693
- Issue date Oct 9, 2001
- Synopsys, Inc.
- William C. Naylor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Non-linear optimization system and method for wire length and densi...
- Patent number 6,282,693
- Issue date Aug 28, 2001
- Synopsys, Inc.
- William C. Naylor
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
PLACEMENT-BASED CONGESTION-AWARE LOGIC RESTRUCTURING
- Publication number 20180121591
- Publication date May 3, 2018
- Synopsys, Inc.
- Jagat B. Patel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Optimizing The Ordering Of The Inputs To Large Commutative-Associat...
- Publication number 20180004862
- Publication date Jan 4, 2018
- Synopsys, Inc.
- Bogdan Craciun
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Detailed Placer For Optimizing High Density Cell Placement In A Lin...
- Publication number 20080250375
- Publication date Oct 9, 2008
- Synopsys, Inc.
- Ronald Miller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Automation method and system for assessing timing based on Gaussian...
- Publication number 20070016881
- Publication date Jan 18, 2007
- Synopsys, Inc.
- Brent Gregory
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Placing cells of an IC design using partition preconditioning
- Publication number 20040230931
- Publication date Nov 18, 2004
- Troy W. Barbee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Simultaneous placement of large and small cells in an electronic ci...
- Publication number 20040225971
- Publication date Nov 11, 2004
- Ross A. Donelly
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Constrained optimization with linear constraints to remove overlap...
- Publication number 20040225982
- Publication date Nov 11, 2004
- Ross A. Donelly
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Detailed placer for optimizing high density cell placement in a lin...
- Publication number 20040078770
- Publication date Apr 22, 2004
- SYNOPSYS, INC.
- Ronald Miller
- G06 - COMPUTING CALCULATING COUNTING

William C. Naylor

Person

Patents Grantslast 30 patents

Boolean satisfiability (SAT) solver

Placement-based congestion-aware logic restructuring

Optimizing the ordering of the inputs to large commutative-associat...

Detailed placer for optimizing high density cell placement in a lin...

Detailed placer for optimizing high density cell placement in a lin...

Detailed placer for optimizing high density cell placement in a lin...

Simultaneous placement of large and small cells in an electronic ci...

Constrained optimization with linear constraints to remove overlap...

Multiple pass optimization for automatic electronic circuit placement

Non-linear optimization system and method for wire length and delay...

Quick placement of electronic circuits using orthogonal one dimensi...

Non-linear optimization system and method for wire length and densi...

Non-linear optimization system and method for wire length and delay...

Non-linear optimization system and method for wire length and densi...

Patents Applicationslast 30 patents

PLACEMENT-BASED CONGESTION-AWARE LOGIC RESTRUCTURING

Optimizing The Ordering Of The Inputs To Large Commutative-Associat...

Detailed Placer For Optimizing High Density Cell Placement In A Lin...

Automation method and system for assessing timing based on Gaussian...

Placing cells of an IC design using partition preconditioning

Simultaneous placement of large and small cells in an electronic ci...

Constrained optimization with linear constraints to remove overlap...

Detailed placer for optimizing high density cell placement in a lin...