William C. Plants

Person

Campbell, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Direct-bonded native interconnects and active base die
- Patent number 11,823,906
- Issue date Nov 21, 2023
- Xcelsis Corporation
- Javier A. Delacruz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Direct-bonded native interconnects and active base die
- Patent number 11,289,333
- Issue date Mar 29, 2022
- Xcelsis Corporation
- Javier A. Delacruz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Direct-bonded native interconnects and active base die
- Patent number 10,832,912
- Issue date Nov 10, 2020
- Xcelsis Corporation
- Javier A. Delacruz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self healing compute array
- Patent number 10,684,929
- Issue date Jun 16, 2020
- Xcelsis Corporation
- Javier A. Delacruz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Direct-bonded native interconnects and active base die
- Patent number 10,522,352
- Issue date Dec 31, 2019
- Xcelsis Corporation
- Javier A. Delacruz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Enhanced memory reliability in stacked memory devices
- Patent number 10,409,677
- Issue date Sep 10, 2019
- Invensas Corporation
- William C. Plants
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Wafer testing without direct probing
- Patent number 10,295,588
- Issue date May 21, 2019
- Xcelsis Corporation
- Javier A. Delacruz
- G01 - MEASURING TESTING
Information Patent Grant
DRAM adjacent row disturb mitigation
- Patent number 10,262,717
- Issue date Apr 16, 2019
- Invensas Corporation
- David Edward Fisch
- G11 - INFORMATION STORAGE
Information Patent Grant
Preferred state encoding in non-volatile memories
- Patent number 10,169,143
- Issue date Jan 1, 2019
- Invensas Corporation
- William C. Plants
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Enhanced memory reliability in stacked memory devices
- Patent number 10,083,079
- Issue date Sep 25, 2018
- Invensas Corporation
- William C. Plants
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
FPGA RAM blocks optimized for use as register files
- Patent number 10,020,811
- Issue date Jul 10, 2018
- MICROSEMI SOC CORP.
- Joel Landry
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Preferred state encoding in non-volatile memories
- Patent number 10,007,573
- Issue date Jun 26, 2018
- Invensas Corporation
- William C. Plants
- G11 - INFORMATION STORAGE
Information Patent Grant
DRAM adjacent row disturb mitigation
- Patent number 9,812,185
- Issue date Nov 7, 2017
- Invensas Corporation
- David Edward Fisch
- G11 - INFORMATION STORAGE
Information Patent Grant
FPGA RAM blocks optimized for use as register files
- Patent number 9,780,792
- Issue date Oct 3, 2017
- MICROSEMI SOC CORP.
- Joel Landry
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Enhanced memory reliability in stacked memory devices
- Patent number 9,778,984
- Issue date Oct 3, 2017
- Invensas Corporation
- William C. Plants
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Retention optimized memory device using predictive data inversion
- Patent number 9,548,101
- Issue date Jan 17, 2017
- Invensas Corporation
- David Edward Fisch
- G11 - INFORMATION STORAGE
Information Patent Grant
Retention optimized memory device using predictive data inversion
- Patent number 9,299,398
- Issue date Mar 29, 2016
- Invensas Corporation
- David Edward Fisch
- G11 - INFORMATION STORAGE
Information Patent Grant
Retention optimized memory device using predictive data inversion
- Patent number 9,007,866
- Issue date Apr 14, 2015
- Tessera Inc.
- David Edward Fisch
- G11 - INFORMATION STORAGE
Information Patent Grant
Common doped region with separate gate control for a logic compatib...
- Patent number 8,873,302
- Issue date Oct 28, 2014
- Invensas Corporation
- David Edward Fisch
- G11 - INFORMATION STORAGE
Information Patent Grant
FPGA RAM blocks optimized for use as register files
- Patent number 8,446,170
- Issue date May 21, 2013
- Actel Corporation
- Joel Landry
- G11 - INFORMATION STORAGE
Information Patent Grant
Enhanced field programmable gate array
- Patent number 8,258,811
- Issue date Sep 4, 2012
- Actel Corporation
- Samuel W. Beal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable delay line compensated for process, voltage, and tempe...
- Patent number 8,067,959
- Issue date Nov 29, 2011
- Actel Corporation
- William C. Plants
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Enhanced field programmable gate array
- Patent number 7,977,970
- Issue date Jul 12, 2011
- Actel Corporation
- Samuel W. Beal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Non-volatile two-transistor programmable logic cell and array layout
- Patent number 7,956,404
- Issue date Jun 7, 2011
- Actel Corporation
- Fethi Dhaoui
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Delay locked loop for an FPGA architecture
- Patent number 7,941,685
- Issue date May 10, 2011
- Actel Corporation
- William C. Plants
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable system on a chip
- Patent number 7,937,601
- Issue date May 3, 2011
- Actel Corporation
- Greg Bakker
- G01 - MEASURING TESTING
Information Patent Grant
Programmable logic device with a microcontroller-based control system
- Patent number 7,924,051
- Issue date Apr 12, 2011
- Actel Corporation
- Gregory Bakker
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Non-volatile two-transistor programmable logic cell and array layout
- Patent number 7,915,665
- Issue date Mar 29, 2011
- Actel Corporation
- Fethi Dhaoui
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Flash-based FPGA with secure reprogramming
- Patent number 7,885,122
- Issue date Feb 8, 2011
- Actel Corporation
- Joel Landry
- G11 - INFORMATION STORAGE
Information Patent Grant
Field programmable gate array and microcontroller system-on-a-chip
- Patent number 7,886,130
- Issue date Feb 8, 2011
- Actel Corporation
- Arunangshu Kundu
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Direct-Bonded Native Interconnects And Active Base Die
- Publication number 20220238339
- Publication date Jul 28, 2022
- Xcelsis Corporation
- Javier A. DELACRUZ
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Direct-Bonded Native Interconnects And Active Base Die
- Publication number 20200357641
- Publication date Nov 12, 2020
- Xcelsis Corporation
- Javier A. DELACRUZ
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DIRECT-BONDED NATIVE INTERCONNECTS AND ACTIVE BASE DIE
- Publication number 20200194262
- Publication date Jun 18, 2020
- Xcelsis Corporation
- Javier A. DELACRUZ
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ENHANCED MEMORY RELIABILITY IN STACKED MEMORY DEVICES
- Publication number 20190012232
- Publication date Jan 10, 2019
- Invensas Corporation
- William C. Plants
- G11 - INFORMATION STORAGE
Information Patent Application
Preferred State Encoding in Non-Volatile Memories
- Publication number 20180232273
- Publication date Aug 16, 2018
- Invensas Corporation
- William C. PLANTS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Wafer Testing Without Direct Probing
- Publication number 20180180665
- Publication date Jun 28, 2018
- Invensas Corporation
- Javier A. DELACRUZ
- G01 - MEASURING TESTING
Information Patent Application
Self Healing Compute Array
- Publication number 20180173600
- Publication date Jun 21, 2018
- Invensas Corporation
- Javier A. DELACRUZ
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Enhanced Memory Reliability in Stacked Memory Devices
- Publication number 20180121283
- Publication date May 3, 2018
- Invensas Corporation
- William C. Plants
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DRAM Adjacent Row Disturb Mitigation
- Publication number 20180114561
- Publication date Apr 26, 2018
- Invensas Corporation
- David Edward Fisch
- G11 - INFORMATION STORAGE
Information Patent Application
Direct-bonded native interconnects and active base die
- Publication number 20180102251
- Publication date Apr 12, 2018
- INVENSAS BONDING TECHNOLOGIES, INC.
- Javier A. DELACRUZ
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FPGA RAM Blocks Optimized for Use as Register Files
- Publication number 20180026641
- Publication date Jan 25, 2018
- Microsemi SoC Corporation
- Joel Landry
- G11 - INFORMATION STORAGE
Information Patent Application
DRAM Adjacent Row Disturb Mitigation
- Publication number 20170117030
- Publication date Apr 27, 2017
- Invensas Corporation
- David Edward Fisch
- G11 - INFORMATION STORAGE
Information Patent Application
PREFERRED STATE ENCODING IN NON-VOLATILE MEMORIES
- Publication number 20160314042
- Publication date Oct 27, 2016
- Invensas Corporation
- William C. PLANTS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Retention optimized memory device using predictive data inversion
- Publication number 20160189765
- Publication date Jun 30, 2016
- Invensas Corporation
- David Edward FISCH
- G11 - INFORMATION STORAGE
Information Patent Application
Retention optimized memory device using predictive data inversion
- Publication number 20150213847
- Publication date Jul 30, 2015
- Invensas Corporation
- David Edward FISCH
- G11 - INFORMATION STORAGE
Information Patent Application
RETENTION OPTIMIZED MEMORY DEVICE USING PREDICTIVE DATA INVERSION
- Publication number 20140313834
- Publication date Oct 23, 2014
- Invensas Corporation
- David Edward FISCH
- G11 - INFORMATION STORAGE
Information Patent Application
FPGA RAM BLOCKS OPTIMIZED FOR USE AS REGISTER FILES
- Publication number 20130271180
- Publication date Oct 17, 2013
- Joel Landry
- G11 - INFORMATION STORAGE
Information Patent Application
COMMON DOPED REGION WITH SEPARATE GATE CONTROL FOR A LOGIC COMPATIB...
- Publication number 20130107635
- Publication date May 2, 2013
- Invensas Corporation
- David Edward Fisch
- G11 - INFORMATION STORAGE
Information Patent Application
FPGA RAM BLOCKS OPTIMIZED FOR USE AS REGISTER FILES
- Publication number 20120280711
- Publication date Nov 8, 2012
- Actel Corporation
- Joel Landry
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
ENHANCED FILED PROGRAMMABLE GATE ARRAY
- Publication number 20110234258
- Publication date Sep 29, 2011
- Actel Corporation
- Samuel W. Beal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
ENHANCED FIELD PROGRAMMABLE GATE ARRAY
- Publication number 20100244894
- Publication date Sep 30, 2010
- Actel Corporation
- Samuel W. Beal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PROGRAMMABLE DELAY LINE COMPENSATED FOR PROCESS, VOLTAGE, AND TEMPE...
- Publication number 20100156459
- Publication date Jun 24, 2010
- Actel Corporation
- William C. Plants
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PROGRAMMABLE LOGIC DEVICE WITH A MICROCONTROLLER-BASED CONTROL SYSTEM
- Publication number 20100134142
- Publication date Jun 3, 2010
- Actel Corporation
- Gregory Bakker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FLEXIBLE CARRY SCHEME FOR FIELD PROGRAMMABLE GATE ARRAYS
- Publication number 20100100864
- Publication date Apr 22, 2010
- Actel Corporation
- William C. Plants
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NON-VOLATILE TWO-TRANSISTOR PROGRAMMABLE LOGIC CELL AND ARRAY LAYOUT
- Publication number 20100038697
- Publication date Feb 18, 2010
- Actel Corporation
- Fethi Dhaoui
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FLASH-BASED FPGA WITH SECURE REPROGRAMMING
- Publication number 20100014357
- Publication date Jan 21, 2010
- Actel Corporation
- Joel Landry
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PROGRAMMABLE SYSTEM ON A CHIP
- Publication number 20090292937
- Publication date Nov 26, 2009
- Actel Corporation
- Greg Bakker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NON-VOLATILE TWO-TRANSISTOR PROGRAMMABLE LOGIC CELL AND ARRAY LAYOUT
- Publication number 20090212343
- Publication date Aug 27, 2009
- Actel Corporation
- Fethi Dhaoui
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FIELD PROGRAMMABLE GATE ARRAY AND MICROCONTROLLER SYSTEM-ON-A-CHIP
- Publication number 20090106531
- Publication date Apr 23, 2009
- Actel Corporation
- Arunangshu Kundu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DELAY LOCKED LOOP FOR AN FPGA ARCHITECTURE
- Publication number 20090094475
- Publication date Apr 9, 2009
- Actel Corporation
- William C. Plants
- G06 - COMPUTING CALCULATING COUNTING

William C. Plants

Person

Patents Grantslast 30 patents

Direct-bonded native interconnects and active base die

Direct-bonded native interconnects and active base die

Direct-bonded native interconnects and active base die

Self healing compute array

Direct-bonded native interconnects and active base die

Enhanced memory reliability in stacked memory devices

Wafer testing without direct probing

DRAM adjacent row disturb mitigation

Preferred state encoding in non-volatile memories

Enhanced memory reliability in stacked memory devices

FPGA RAM blocks optimized for use as register files

Preferred state encoding in non-volatile memories

DRAM adjacent row disturb mitigation

FPGA RAM blocks optimized for use as register files

Enhanced memory reliability in stacked memory devices

Retention optimized memory device using predictive data inversion

Retention optimized memory device using predictive data inversion

Retention optimized memory device using predictive data inversion

Common doped region with separate gate control for a logic compatib...

FPGA RAM blocks optimized for use as register files

Enhanced field programmable gate array

Programmable delay line compensated for process, voltage, and tempe...

Enhanced field programmable gate array

Non-volatile two-transistor programmable logic cell and array layout

Delay locked loop for an FPGA architecture

Programmable system on a chip

Programmable logic device with a microcontroller-based control system

Non-volatile two-transistor programmable logic cell and array layout

Flash-based FPGA with secure reprogramming

Field programmable gate array and microcontroller system-on-a-chip

Patents Applicationslast 30 patents

Direct-Bonded Native Interconnects And Active Base Die

Direct-Bonded Native Interconnects And Active Base Die

DIRECT-BONDED NATIVE INTERCONNECTS AND ACTIVE BASE DIE

ENHANCED MEMORY RELIABILITY IN STACKED MEMORY DEVICES

Preferred State Encoding in Non-Volatile Memories

Wafer Testing Without Direct Probing

Self Healing Compute Array

Enhanced Memory Reliability in Stacked Memory Devices

DRAM Adjacent Row Disturb Mitigation

Direct-bonded native interconnects and active base die

FPGA RAM Blocks Optimized for Use as Register Files

DRAM Adjacent Row Disturb Mitigation

PREFERRED STATE ENCODING IN NON-VOLATILE MEMORIES

Retention optimized memory device using predictive data inversion

Retention optimized memory device using predictive data inversion

RETENTION OPTIMIZED MEMORY DEVICE USING PREDICTIVE DATA INVERSION

FPGA RAM BLOCKS OPTIMIZED FOR USE AS REGISTER FILES

COMMON DOPED REGION WITH SEPARATE GATE CONTROL FOR A LOGIC COMPATIB...

FPGA RAM BLOCKS OPTIMIZED FOR USE AS REGISTER FILES

ENHANCED FILED PROGRAMMABLE GATE ARRAY

ENHANCED FIELD PROGRAMMABLE GATE ARRAY

PROGRAMMABLE DELAY LINE COMPENSATED FOR PROCESS, VOLTAGE, AND TEMPE...

PROGRAMMABLE LOGIC DEVICE WITH A MICROCONTROLLER-BASED CONTROL SYSTEM

FLEXIBLE CARRY SCHEME FOR FIELD PROGRAMMABLE GATE ARRAYS

NON-VOLATILE TWO-TRANSISTOR PROGRAMMABLE LOGIC CELL AND ARRAY LAYOUT

FLASH-BASED FPGA WITH SECURE REPROGRAMMING

PROGRAMMABLE SYSTEM ON A CHIP

NON-VOLATILE TWO-TRANSISTOR PROGRAMMABLE LOGIC CELL AND ARRAY LAYOUT

FIELD PROGRAMMABLE GATE ARRAY AND MICROCONTROLLER SYSTEM-ON-A-CHIP

DELAY LOCKED LOOP FOR AN FPGA ARCHITECTURE