William Chad Waldrop

Person

Allen, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Apparatuses and methods for a per-DRAM addressability synchronizer...
- Patent number 12,183,385
- Issue date Dec 31, 2024
- Micron Technology, Inc.
- William C. Waldrop
- G11 - INFORMATION STORAGE
Information Patent Grant
Synchronous input buffer enable for DFE operation
- Patent number 11,996,162
- Issue date May 28, 2024
- Micron Technology, Inc.
- William C. Waldrop
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods of reducing clock domain crossing timing violations, and re...
- Patent number 11,727,979
- Issue date Aug 15, 2023
- Micron Technology, Inc.
- Kallol Mazumder
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Write interamble counter
- Patent number 11,495,281
- Issue date Nov 8, 2022
- Micron Technology, Inc.
- William C. Waldrop
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods for parity error alert timing interlock and memory devices...
- Patent number 11,487,610
- Issue date Nov 1, 2022
- Micron Technology, Inc.
- William C. Waldrop
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reset speed modulation circuitry for a decision feedback equalizer...
- Patent number 11,417,374
- Issue date Aug 16, 2022
- Micron Technology, Inc.
- William Chad Waldrop
- G11 - INFORMATION STORAGE
Information Patent Grant
Metastable resistant latch
- Patent number 11,264,078
- Issue date Mar 1, 2022
- Micron Technology, Inc.
- Daniel B. Penney
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Centralized DFE reset generator for a memory device
- Patent number 11,145,353
- Issue date Oct 12, 2021
- Micron Technology, Inc.
- William Chad Waldrop
- G11 - INFORMATION STORAGE
Information Patent Grant
Reduced shifter memory system
- Patent number 10,872,658
- Issue date Dec 22, 2020
- Micron Technology, Inc.
- Jason M. Brown
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Parallel error calculation
- Patent number 10,838,799
- Issue date Nov 17, 2020
- Micron Technology, Inc.
- William C. Waldrop
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for controlling semiconductor device wear
- Patent number 10,840,908
- Issue date Nov 17, 2020
- Micron Technology, Inc.
- William C. Waldrop
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Methods for parity error synchronization and memory devices and sys...
- Patent number 10,783,980
- Issue date Sep 22, 2020
- Micron Technology, Inc.
- William C. Waldrop
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for controlling semiconductor device wear
- Patent number 10,447,267
- Issue date Oct 15, 2019
- Micron Technology, Inc.
- William C. Waldrop
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Reduced shifter memory system
- Patent number 10,354,717
- Issue date Jul 16, 2019
- Micron Technology, Inc.
- Jason M. Brown
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for threshold voltage modification and detection
- Patent number 10,269,441
- Issue date Apr 23, 2019
- Micron Technology, Inc.
- Daniel B. Penney
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Systems and methods for threshold voltage modification and detection
- Patent number 10,127,994
- Issue date Nov 13, 2018
- Micron Technology, Inc.
- Daniel B. Penney
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and apparatus for selecting an operating mode based on a det...
- Patent number 9,479,361
- Issue date Oct 25, 2016
- Micron Technology, Inc.
- William C. Waldrop
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and apparatus for selecting an operating mode based on a det...
- Patent number 7,915,924
- Issue date Mar 29, 2011
- Micron Technology, Inc.
- William C. Waldrop
- G11 - INFORMATION STORAGE
Information Patent Grant
Pre-driver logic
- Patent number 7,898,294
- Issue date Mar 1, 2011
- Micron Technology, Inc.
- William Chad Waldrop
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Pre-driver logic
- Patent number 7,675,324
- Issue date Mar 9, 2010
- Micron Technology, Inc.
- William Chad Waldrop
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for selecting an operating mode based on a det...
- Patent number 7,560,956
- Issue date Jul 14, 2009
- Micron Technology, Inc.
- William C. Waldrop
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable dual drive strength output buffer with a shared boot c...
- Patent number 7,230,457
- Issue date Jun 12, 2007
- Micron Technology, Inc.
- William C. Waldrop
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and circuit for adjusting the timing of output data based on...
- Patent number 6,975,149
- Issue date Dec 13, 2005
- Micron Technology, Inc.
- Vladimir Mikhalev
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable dual-drive strength output buffer with a shared boot c...
- Patent number 6,885,226
- Issue date Apr 26, 2005
- Micron Technology, Inc.
- William C. Waldrop
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and circuit for adjusting the timing of output data based on...
- Patent number 6,819,151
- Issue date Nov 16, 2004
- Micron Technology, Inc.
- Vladimir Mikhalev
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and circuit for adjusting the timing of output data based on...
- Patent number 6,693,472
- Issue date Feb 17, 2004
- Micron Technology, Inc.
- Vladimir Mikhalev
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and circuit for adjusting the timing of ouput data based on...
- Patent number 6,605,969
- Issue date Aug 12, 2003
- Micron Technology, Inc.
- Vladimir Mikhalev
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable dual drive strength output buffer with a shared boot c...
- Patent number 6,559,690
- Issue date May 6, 2003
- Micron Technology, Inc.
- William C. Waldrop
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Scheme for delay locked loop reset protection
- Patent number 6,549,041
- Issue date Apr 15, 2003
- Micron Technology, Inc.
- William C. Waldrop
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Scheme for delay locked loop reset protection
- Patent number 6,452,431
- Issue date Sep 17, 2002
- Micron Technology, Inc.
- William C. Waldrop
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
DATA INPUT BUFFER WITH A BRANCHED DFE RESET PATH
- Publication number 20240347102
- Publication date Oct 17, 2024
- Micron Technology, Inc.
- William Chad Waldrop
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUSES AND METHODS FOR A PER-DRAM ADDRESSABILITY SYNCHRONIZER...
- Publication number 20240062803
- Publication date Feb 22, 2024
- Micron Technology, Inc.
- William C. Waldrop
- G11 - INFORMATION STORAGE
Information Patent Application
Synchronous Input Buffer Control Using a Write Shifter
- Publication number 20240005980
- Publication date Jan 4, 2024
- Micron Technology, Inc.
- William Chad Waldrop
- G11 - INFORMATION STORAGE
Information Patent Application
SYNCHRONOUS INPUT BUFFER ENABLE FOR DFE OPERATION
- Publication number 20230395105
- Publication date Dec 7, 2023
- Micron Technology, Inc.
- William C. Waldrop
- G11 - INFORMATION STORAGE
Information Patent Application
METHODS OF REDUCING CLOCK DOMAIN CROSSING TIMING VIOLATIONS, AND RE...
- Publication number 20230007872
- Publication date Jan 12, 2023
- Micron Technology, Inc.
- Kallol Mazumder
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RESET SPEED MODULATION CIRCUITRY FOR A DECISION FEEDBACK EQUALIZER...
- Publication number 20220262413
- Publication date Aug 18, 2022
- Micron Technology, Inc.
- William Chad Waldrop
- G11 - INFORMATION STORAGE
Information Patent Application
CENTRALIZED DFE RESET GENERATOR FOR A MEMORY DEVICE
- Publication number 20210319826
- Publication date Oct 14, 2021
- Micron Technology, Inc.
- William Chad Waldrop
- G11 - INFORMATION STORAGE
Information Patent Application
WRITE INTERAMBLE COUNTER
- Publication number 20210304809
- Publication date Sep 30, 2021
- Micron Technology, Inc.
- William C. Waldrop
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PARALLEL ERROR CALCULATION
- Publication number 20200057688
- Publication date Feb 20, 2020
- Micron Technology, Inc.
- William C. Waldrop
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR CONTROLLING SEMICONDUCTOR DEVICE WEAR
- Publication number 20200059235
- Publication date Feb 20, 2020
- Micron Technology, Inc.
- William C. Waldrop
- G11 - INFORMATION STORAGE
Information Patent Application
REDUCED SHIFTER MEMORY SYSTEM
- Publication number 20190348105
- Publication date Nov 14, 2019
- Micron Technology, Inc.
- Jason M. Brown
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS FOR PARITY ERROR SYNCHRONIZATION AND MEMORY DEVICES AND SYS...
- Publication number 20190348139
- Publication date Nov 14, 2019
- Micron Technology, Inc.
- William C. Waldrop
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS FOR PARITY ERROR ALERT TIMING INTERLOCK AND MEMORY DEVICES...
- Publication number 20190347157
- Publication date Nov 14, 2019
- Micron Technology, Inc.
- William C. Waldrop
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR THRESHOLD VOLTAGE MODIFICATION AND DETECTION
- Publication number 20190122742
- Publication date Apr 25, 2019
- Micron Technology, Inc.
- Daniel B. Penney
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND APPARATUS FOR SELECTING AN OPERATING MODE BASED ON A DET...
- Publication number 20110169529
- Publication date Jul 14, 2011
- Micron Technology, Inc.
- William C. Waldrop
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
PRE-DRIVER LOGIC
- Publication number 20100156463
- Publication date Jun 24, 2010
- Micron Technology, Inc.
- William Chad Waldrop
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Method and Apparatus for Selecting an Operating Mode Based on a Det...
- Publication number 20090302892
- Publication date Dec 10, 2009
- Micron Technology, Inc.
- William C. Waldrop
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
PRE-DRIVER LOGIC
- Publication number 20090153191
- Publication date Jun 18, 2009
- Micron Technology, Inc.
- WILLIAM CHAD WALDROP
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Method and apparatus for selecting an operating mode based on a det...
- Publication number 20070030030
- Publication date Feb 8, 2007
- Micron Technology, Inc.
- William C. Waldrop
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Time domain bridging circuitry for use in determining output enable...
- Publication number 20070008758
- Publication date Jan 11, 2007
- Micron Technology, Inc.
- William Chad Waldrop
- G11 - INFORMATION STORAGE
Information Patent Application
Programmable dual drive strength output buffer with a shared boot c...
- Publication number 20050068071
- Publication date Mar 31, 2005
- Micron Technology, Inc.
- William C. Waldrop
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Method and circuit for adjusting the timing of output data based on...
- Publication number 20050035799
- Publication date Feb 17, 2005
- Vladimir Mikhalev
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Method and circuit for adjusting the timing of output data based on...
- Publication number 20040036515
- Publication date Feb 26, 2004
- Vladimir Mikhalev
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Programmable dual-drive strength output buffer with a shared boot c...
- Publication number 20030201804
- Publication date Oct 30, 2003
- Micron Technology, Inc.
- William C. Waldrop
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Method and circuit for adjusting the timing of ouput data based on...
- Publication number 20030067330
- Publication date Apr 10, 2003
- Vladimir Mikhalev
- G11 - INFORMATION STORAGE
Information Patent Application
Method and circuit for adjusting the timing of output data based on...
- Publication number 20030067332
- Publication date Apr 10, 2003
- Vladimir Mikhalev
- G11 - INFORMATION STORAGE
Information Patent Application
Scheme for delay locked loop reset protection
- Publication number 20020190766
- Publication date Dec 19, 2002
- Micron Technology, Inc.
- William C. Waldrop
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Programmable dual drive strength output buffer with a shared boot c...
- Publication number 20020130690
- Publication date Sep 19, 2002
- William C. Waldrop
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

William Chad Waldrop

Person

Patents Grantslast 30 patents

Apparatuses and methods for a per-DRAM addressability synchronizer...

Synchronous input buffer enable for DFE operation

Methods of reducing clock domain crossing timing violations, and re...

Write interamble counter

Methods for parity error alert timing interlock and memory devices...

Reset speed modulation circuitry for a decision feedback equalizer...

Metastable resistant latch

Centralized DFE reset generator for a memory device

Reduced shifter memory system

Parallel error calculation

Systems and methods for controlling semiconductor device wear

Methods for parity error synchronization and memory devices and sys...

Systems and methods for controlling semiconductor device wear

Reduced shifter memory system

Systems and methods for threshold voltage modification and detection

Systems and methods for threshold voltage modification and detection

Method and apparatus for selecting an operating mode based on a det...

Method and apparatus for selecting an operating mode based on a det...

Pre-driver logic

Pre-driver logic

Method and apparatus for selecting an operating mode based on a det...

Programmable dual drive strength output buffer with a shared boot c...

Method and circuit for adjusting the timing of output data based on...

Programmable dual-drive strength output buffer with a shared boot c...

Method and circuit for adjusting the timing of output data based on...

Method and circuit for adjusting the timing of output data based on...

Method and circuit for adjusting the timing of ouput data based on...

Programmable dual drive strength output buffer with a shared boot c...

Scheme for delay locked loop reset protection

Scheme for delay locked loop reset protection

Patents Applicationslast 30 patents

DATA INPUT BUFFER WITH A BRANCHED DFE RESET PATH

APPARATUSES AND METHODS FOR A PER-DRAM ADDRESSABILITY SYNCHRONIZER...

Synchronous Input Buffer Control Using a Write Shifter

SYNCHRONOUS INPUT BUFFER ENABLE FOR DFE OPERATION

METHODS OF REDUCING CLOCK DOMAIN CROSSING TIMING VIOLATIONS, AND RE...

RESET SPEED MODULATION CIRCUITRY FOR A DECISION FEEDBACK EQUALIZER...

CENTRALIZED DFE RESET GENERATOR FOR A MEMORY DEVICE

WRITE INTERAMBLE COUNTER

PARALLEL ERROR CALCULATION

SYSTEMS AND METHODS FOR CONTROLLING SEMICONDUCTOR DEVICE WEAR

REDUCED SHIFTER MEMORY SYSTEM

METHODS FOR PARITY ERROR SYNCHRONIZATION AND MEMORY DEVICES AND SYS...

METHODS FOR PARITY ERROR ALERT TIMING INTERLOCK AND MEMORY DEVICES...

SYSTEMS AND METHODS FOR THRESHOLD VOLTAGE MODIFICATION AND DETECTION

METHOD AND APPARATUS FOR SELECTING AN OPERATING MODE BASED ON A DET...

PRE-DRIVER LOGIC

Method and Apparatus for Selecting an Operating Mode Based on a Det...

PRE-DRIVER LOGIC

Method and apparatus for selecting an operating mode based on a det...

Time domain bridging circuitry for use in determining output enable...

Programmable dual drive strength output buffer with a shared boot c...

Method and circuit for adjusting the timing of output data based on...

Method and circuit for adjusting the timing of output data based on...

Programmable dual-drive strength output buffer with a shared boot c...

Method and circuit for adjusting the timing of ouput data based on...

Method and circuit for adjusting the timing of output data based on...

Scheme for delay locked loop reset protection

Programmable dual drive strength output buffer with a shared boot c...