William Chou

Person

Cupertino, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Multi-layer opto-electronic substrates with electrical and optical...
- Patent number 6,845,184
- Issue date Jan 18, 2005
- Fujitsu Limited
- Tetsuzo Yoshimura
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of planarizing structures on wafers and substrates by polis...
- Patent number 6,733,685
- Issue date May 11, 2004
- Fujitsu Limited
- Solomon I. Beilin
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Three-dimensional opto-electronic modules with electrical and optic...
- Patent number 6,690,845
- Issue date Feb 10, 2004
- Fujitsu Limited
- Tetsuzo Yoshimura
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Method of fabricating a substrate with a via connection
- Patent number 6,662,443
- Issue date Dec 16, 2003
- Fujitsu Limited
- William T. Chou
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Opto-electronic substrates with electrical and optical interconnect...
- Patent number 6,611,635
- Issue date Aug 26, 2003
- Fujitsu Limited
- Tetsuzo Yoshimura
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Systems based on opto-electronic substrates with electrical and opt...
- Patent number 6,343,171
- Issue date Jan 29, 2002
- Fujitsu Limited
- Tetsuzo Yoshimura
- G02 - OPTICS
Information Patent Grant
Reduced cross-talk noise high density signal interposer with power...
- Patent number 6,239,485
- Issue date May 29, 2001
- Fujitsu Limited
- Michael G. Peters
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Power conducting substrates with high-yield integrated substrate ca...
- Patent number 6,226,171
- Issue date May 1, 2001
- Fujitsu Limited
- Solomon I. Beilin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of patterning polyamic acid layers
- Patent number 6,221,567
- Issue date Apr 24, 2001
- Fujitsu Limited
- Solomon I. Beilin
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Method for electroplating vias or through holes in substrates havin...
- Patent number 6,197,664
- Issue date Mar 6, 2001
- Fujitsu Limited
- Michael G. Lee
- C25 - ELECTROLYTIC OR ELECTROPHORETIC PROCESSES APPARATUS THEREFOR
Information Patent Grant
Method of fabrication of multiple-layer high density substrate
- Patent number 6,187,652
- Issue date Feb 13, 2001
- Fujitsu Limited
- William T. Chou
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Controlled impedance interposer substrate and method of making
- Patent number 6,102,710
- Issue date Aug 15, 2000
- Fujitsu Limited
- Solomon I. Beilin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High density signal interposer with power and ground wrap
- Patent number 6,081,026
- Issue date Jun 27, 2000
- Fujitsu Limited
- Wen-chou Vincent Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process flows for formation of fine structure layer pairs on flexib...
- Patent number 6,039,889
- Issue date Mar 21, 2000
- Fujitsu Limited
- Lei Zhang
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Pattern or via structure formed through supplemental electron beam...
- Patent number 5,942,373
- Issue date Aug 24, 1999
- Fujitsu Limited
- William T. Chou
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Structure and fabrication procedure for a stable post
- Patent number 5,930,890
- Issue date Aug 3, 1999
- Fujitsu Limited
- William T. Chou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of planarizing structures on wafers and substrates by polis...
- Patent number 5,916,453
- Issue date Jun 29, 1999
- Fujitsu Limited
- Solomon I. Beilin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of etching through wafers and substrates with a composite e...
- Patent number 5,891,354
- Issue date Apr 6, 1999
- Fujitsu Limited
- Michael G. Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Controlled impedence interposer substrate
- Patent number 5,854,534
- Issue date Dec 29, 1998
- Fujitsu Limited
- Solomon I. Beilin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming a pattern or via structure utilizing supplemental...
- Patent number 5,789,140
- Issue date Aug 4, 1998
- Fujitsu Limited
- William T. Chou
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Method of making a multichip module substrate
- Patent number 5,778,529
- Issue date Jul 14, 1998
- Fujitsu Limited
- Solomon I. Beilin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wire interconnect structures for connecting an integrated circuit t...
- Patent number 5,773,889
- Issue date Jun 30, 1998
- Fujitsu Limited
- David George Love
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wet chemical processing techniques for plating high aspect ratio fe...
- Patent number 5,746,903
- Issue date May 5, 1998
- Fujitsu Limited
- Solomon I. Beilin
- C25 - ELECTROLYTIC OR ELECTROPHORETIC PROCESSES APPARATUS THEREFOR
Information Patent Grant
Fabrication procedure for a stable post
- Patent number 5,722,162
- Issue date Mar 3, 1998
- Fujitsu Limited
- William T. Chou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electron-beam treatment procedure for patterned mask layers
- Patent number 5,660,957
- Issue date Aug 26, 1997
- Fujitsu Limited
- William T. Chou
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Methods of forming tall, high-aspect ratio vias and trenches in pho...
- Patent number 5,656,414
- Issue date Aug 12, 1997
- Fujitsu Limited
- William Tai-Hua Chou
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Substrate with thin film capacitor and insulating plug
- Patent number 5,652,693
- Issue date Jul 29, 1997
- Fujitsu Limited
- William T. Chou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multichip module substrate
- Patent number 5,544,017
- Issue date Aug 6, 1996
- Fujitsu Limited
- Solomon I. Beilin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wire interconnect structures for connecting an integrated circuit t...
- Patent number 5,536,362
- Issue date Jul 16, 1996
- Fujitsu Limited
- David G. Love
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Functional substrates for packaging semiconductor chips
- Patent number 5,475,262
- Issue date Dec 12, 1995
- Fujitsu Limited
- Wen-chou V. Wang
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Method of fabricating a substrate with a via connection
- Publication number 20020000037
- Publication date Jan 3, 2002
- William T. Chou
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Application
Methods of planarizing structures on wafers and substrates by polis...
- Publication number 20010042734
- Publication date Nov 22, 2001
- Solomon I. Beilin
- H01 - BASIC ELECTRIC ELEMENTS

William Chou

Person

Patents Grantslast 30 patents

Multi-layer opto-electronic substrates with electrical and optical...

Methods of planarizing structures on wafers and substrates by polis...

Three-dimensional opto-electronic modules with electrical and optic...

Method of fabricating a substrate with a via connection

Opto-electronic substrates with electrical and optical interconnect...

Systems based on opto-electronic substrates with electrical and opt...

Reduced cross-talk noise high density signal interposer with power...

Power conducting substrates with high-yield integrated substrate ca...

Method of patterning polyamic acid layers

Method for electroplating vias or through holes in substrates havin...

Method of fabrication of multiple-layer high density substrate

Controlled impedance interposer substrate and method of making

High density signal interposer with power and ground wrap

Process flows for formation of fine structure layer pairs on flexib...

Pattern or via structure formed through supplemental electron beam...

Structure and fabrication procedure for a stable post

Methods of planarizing structures on wafers and substrates by polis...

Methods of etching through wafers and substrates with a composite e...

Controlled impedence interposer substrate

Method of forming a pattern or via structure utilizing supplemental...

Method of making a multichip module substrate

Wire interconnect structures for connecting an integrated circuit t...

Wet chemical processing techniques for plating high aspect ratio fe...

Fabrication procedure for a stable post

Electron-beam treatment procedure for patterned mask layers

Methods of forming tall, high-aspect ratio vias and trenches in pho...

Substrate with thin film capacitor and insulating plug

Multichip module substrate

Wire interconnect structures for connecting an integrated circuit t...

Functional substrates for packaging semiconductor chips

Patents Applicationslast 30 patents

Method of fabricating a substrate with a via connection

Methods of planarizing structures on wafers and substrates by polis...