William Henry Radke

Person

San Francisco, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Stopping criteria for layered iterative error correction
- Patent number 11,405,058
- Issue date Aug 2, 2022
- Micron Technology, Inc.
- Mustafa N. Kaynak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Stopping criteria for layered iterative error correction
- Patent number 10,998,923
- Issue date May 4, 2021
- Micron Technology, Inc.
- Mustafa N. Kaynak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory devices having differently configured blocks of memory cells
- Patent number 10,891,188
- Issue date Jan 12, 2021
- Micron Technology, Inc.
- William H. Radke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory devices having differently configured blocks of memory cells
- Patent number 10,891,187
- Issue date Jan 12, 2021
- Micron Technology, Inc.
- William H. Radke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dual-sided memory module with channels aligned in opposition
- Patent number 10,804,243
- Issue date Oct 13, 2020
- Apple Inc.
- James D. Kelly
- G11 - INFORMATION STORAGE
Information Patent Grant
State change in systems having devices coupled in a chained configu...
- Patent number 10,762,003
- Issue date Sep 1, 2020
- Micron Technology, Inc.
- William H. Radke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Chained bus memory device
- Patent number 10,664,411
- Issue date May 26, 2020
- Micron Technology, Inc.
- Victor Tsai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory devices having differently configured blocks of memory cells
- Patent number 10,409,673
- Issue date Sep 10, 2019
- Micron Technology, Inc.
- William H. Radke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dual-sided memory module with channels aligned in opposition
- Patent number 10,217,721
- Issue date Feb 26, 2019
- Apple Inc.
- James D. Kelly
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stopping criteria for layered iterative error correction
- Patent number 10,193,577
- Issue date Jan 29, 2019
- Micron Technology, Inc.
- Mustafa N. Kaynak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
State change in systems having devices coupled in a chained configu...
- Patent number 10,089,250
- Issue date Oct 2, 2018
- Micron Technology, Inc.
- William H. Radke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dual-ported PCI express-based storage cartridge including single-po...
- Patent number 10,082,957
- Issue date Sep 25, 2018
- Western Digital Technologies, Inc.
- Pinchas Herman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Inferring threshold voltage distributions associated with memory ce...
- Patent number 10,068,655
- Issue date Sep 4, 2018
- Micron Technology, Inc.
- Zhenlei Shen
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatuses and methods including error correction code organization
- Patent number 9,983,928
- Issue date May 29, 2018
- Micron Technology, Inc.
- William Henry Radke
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Packet deconstruction/reconstruction and link-control
- Patent number 9,929,967
- Issue date Mar 27, 2018
- Micron Technology, Inc.
- William H. Radke
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
High density server storage unit
- Patent number 9,901,010
- Issue date Feb 20, 2018
- Skyera, LLC
- Pinchas Herman
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Systems and methods for packaging high density SSDs
- Patent number 9,891,675
- Issue date Feb 13, 2018
- Western Digital Technologies, Inc.
- Pinchas Herman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods for controlling host memory access with memory devices and...
- Patent number 9,811,258
- Issue date Nov 7, 2017
- Micron Technology, Inc.
- Neal A. Galbo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Inferring threshold voltage distributions associated with memory ce...
- Patent number 9,779,828
- Issue date Oct 3, 2017
- Micron Technology, Inc.
- Zhenlei Shen
- G11 - INFORMATION STORAGE
Information Patent Grant
Power consumption control
- Patent number 9,766,830
- Issue date Sep 19, 2017
- Micron Technology, Inc.
- Krishnam R. Datla
- G11 - INFORMATION STORAGE
Information Patent Grant
Multiple engine sequencer
- Patent number 9,702,305
- Issue date Jul 11, 2017
- Micron Technology, Inc.
- William H. Radke
- F02 - COMBUSTION ENGINES HOT-GAS OR COMBUSTION-PRODUCT ENGINE PLANTS
Information Patent Grant
Memory devices and systems configured to adjust a size of an ECC co...
- Patent number 9,654,141
- Issue date May 16, 2017
- Micron Technology, Inc.
- William H. Radke
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Apparatus and method for accessing a non-volatile memory blade usin...
- Patent number 9,645,940
- Issue date May 9, 2017
- Skyera, LLC
- Radoslav Danilak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory apparatus, systems, and methods
- Patent number 9,646,683
- Issue date May 9, 2017
- Micron Technology, Inc.
- Violante Moschiano
- G11 - INFORMATION STORAGE
Information Patent Grant
Chained bus method
- Patent number 9,606,885
- Issue date Mar 28, 2017
- Micron Technology, Inc.
- Victor Tsai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for securing high density SSDs
- Patent number 9,600,038
- Issue date Mar 21, 2017
- Skyera, LLC
- Pinchas Herman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configuring and reconfiguring blocks of memory cells to store user...
- Patent number 9,594,676
- Issue date Mar 14, 2017
- Micron Technology, Inc.
- William H. Radke
- G11 - INFORMATION STORAGE
Information Patent Grant
Host controller
- Patent number 9,588,697
- Issue date Mar 7, 2017
- Micron Technology, Inc.
- Peter Feeley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High capacity storage unit
- Patent number 9,585,290
- Issue date Feb 28, 2017
- Skyera, LLC
- Pinchas Herman
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Memory cell coupling compensation
- Patent number 9,552,257
- Issue date Jan 24, 2017
- Micron Technology, Inc.
- Zhenlei Shen
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
LAYOUT FOR DUAL IN-LINE MEMORY TO SUPPORT 128-BYTE CACHE LINE PROCE...
- Publication number 20230132146
- Publication date Apr 27, 2023
- TACHYUM LTD.
- Radoslav DANILAK
- G11 - INFORMATION STORAGE
Information Patent Application
STOPPING CRITERIA FOR LAYERED ITERATIVE ERROR CORRECTION
- Publication number 20210258022
- Publication date Aug 19, 2021
- Micron Technology, Inc.
- Mustafa N. Kaynak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICES HAVING DIFFERENTLY CONFIGURED BLOCKS OF MEMORY CELLS
- Publication number 20190340066
- Publication date Nov 7, 2019
- Micron Technology, Inc.
- William H. RADKE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICES HAVING DIFFERENTLY CONFIGURED BLOCKS OF MEMORY CELLS
- Publication number 20190340065
- Publication date Nov 7, 2019
- Micron Technology, Inc.
- William H. RADKE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DUAL-SIDED MEMORY MODULE WITH CHANNELS ALIGNED IN OPPOSITION
- Publication number 20190198480
- Publication date Jun 27, 2019
- Apple Inc.
- James D. Kelly
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STOPPING CRITERIA FOR LAYERED ITERATIVE ERROR CORRECTION
- Publication number 20190149175
- Publication date May 16, 2019
- Micron Technology, Inc.
- Mustafa N. Kaynak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STATE CHANGE IN SYSTEMS HAVING DEVICES COUPLED IN A CHAINED CONFIGU...
- Publication number 20180373650
- Publication date Dec 27, 2018
- Micron Technology, Inc.
- William H. Radke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DUAL-SIDED MEMORY MODULE WITH CHANNELS ALIGNED IN OPPOSITION
- Publication number 20180323169
- Publication date Nov 8, 2018
- Apple Inc.
- James D. Kelly
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DUAL-PORTED PCI EXPRESS-BASED STORAGE CARTRIDGE INCLUDING SINGLE-PO...
- Publication number 20180024743
- Publication date Jan 25, 2018
- WESTERN DIGITAL TECHNOLOGIES, INC.
- Pinchas Herman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INFERRING THRESHOLD VOLTAGE DISTRIBUTIONS ASSOCIATED WITH MEMORY CE...
- Publication number 20170358366
- Publication date Dec 14, 2017
- Micron Technology, Inc.
- Zhenlei Shen
- G11 - INFORMATION STORAGE
Information Patent Application
CHAINED BUS METHOD
- Publication number 20170199828
- Publication date Jul 13, 2017
- Micron Technology, Inc.
- Victor Tsai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICES HAVING DIFFERENTLY CONFIGURED BLOCKS OF MEMORY CELLS
- Publication number 20170132073
- Publication date May 11, 2017
- Micron Technology, Inc.
- William H. RADKE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POWER CONSUMPTION CONTROL
- Publication number 20160274812
- Publication date Sep 22, 2016
- Micron Technology, Inc.
- Krishnam R. Datla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUSES AND METHODS INCLUDING ERROR CORRECTION CODE ORGANIZATION
- Publication number 20160253237
- Publication date Sep 1, 2016
- Micron Technology, Inc.
- William Henry Radke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR ACCESSING A NON-VOLATILE MEMORY BLADE USIN...
- Publication number 20160253268
- Publication date Sep 1, 2016
- Skyera, LLC
- Radoslav DANILAK
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INFERRING THRESHOLD VOLTAGE DISTRIBUTIONS ASSOCIATED WITH MEMORY CE...
- Publication number 20160217867
- Publication date Jul 28, 2016
- Micron Technology, Inc.
- Zhenlei Shen
- G11 - INFORMATION STORAGE
Information Patent Application
SYSTEMS AND METHODS FOR PACKAGING HIGH DENSITY SSDS
- Publication number 20160209889
- Publication date Jul 21, 2016
- Skyera, LLC
- Pinchas HERMAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY CELL COUPLING COMPENSATION
- Publication number 20160203048
- Publication date Jul 14, 2016
- Micron Technology, Inc.
- Zhenlei Shen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH DENSITY SERVER STORAGE UNIT
- Publication number 20160205813
- Publication date Jul 14, 2016
- HGST NETHERLANDS B.V.
- Pinchas HERMAN
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
DYNAMIC PROGRAM WINDOW DETERMINATION IN A MEMORY DEVICE
- Publication number 20160203875
- Publication date Jul 14, 2016
- Micron Technology, Inc.
- Tommaso Vali
- G11 - INFORMATION STORAGE
Information Patent Application
STATE CHANGE IN SYSTEMS HAVING DEVICES COUPLED IN A CHAINED CONFIGU...
- Publication number 20160154747
- Publication date Jun 2, 2016
- Micron Technology, Inc.
- William H. Radke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR ROUTING INFORMATION IN A NON-VOLATILE MEMO...
- Publication number 20160110104
- Publication date Apr 21, 2016
- Skyera, LLC
- Radoslav DANILAK
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HOST CONTROLLER
- Publication number 20160004436
- Publication date Jan 7, 2016
- Micron Technology, Inc.
- Peter Feeley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC PROGRAM WINDOW DETERMINATION IN A MEMORY DEVICE
- Publication number 20150348643
- Publication date Dec 3, 2015
- Micron Technology, Inc.
- Tommaso Vali
- G11 - INFORMATION STORAGE
Information Patent Application
STOPPING CRITERIA FOR LAYERED ITERATIVE ERROR CORRECTION
- Publication number 20150333774
- Publication date Nov 19, 2015
- Micron Technology, Inc.
- Mustafa N. Kaynak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY APPARATUS, SYSTEMS, AND METHODS
- Publication number 20150325309
- Publication date Nov 12, 2015
- Micron Technology, Inc.
- Violante Moschiano
- G11 - INFORMATION STORAGE
Information Patent Application
STATE CHANGE IN SYSTEMS HAVING DEVICES COUPLED IN A CHAINED CONFIGU...
- Publication number 20150301746
- Publication date Oct 22, 2015
- Micron Technology, Inc.
- William H. Radke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DETERMINING AND USING SOFT DATA IN MEMORY DEVICES AND SYSTEMS
- Publication number 20150255163
- Publication date Sep 10, 2015
- Micron Technology, Inc.
- William H. Radke
- G11 - INFORMATION STORAGE
Information Patent Application
THRESHOLD VOLTAGE COMPENSATION IN A MEMORY
- Publication number 20150243351
- Publication date Aug 27, 2015
- Micron Technology, Inc.
- Violante Moschiano
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY CONTROLLER SUPPORTING RATE-COMPATIBLE PUNCTURED CODES
- Publication number 20150234704
- Publication date Aug 20, 2015
- Micron Technology, Inc.
- William H. Radke
- G06 - COMPUTING CALCULATING COUNTING

William Henry Radke

Person

Patents Grantslast 30 patents

Stopping criteria for layered iterative error correction

Stopping criteria for layered iterative error correction

Memory devices having differently configured blocks of memory cells

Memory devices having differently configured blocks of memory cells

Dual-sided memory module with channels aligned in opposition

State change in systems having devices coupled in a chained configu...

Chained bus memory device

Memory devices having differently configured blocks of memory cells

Dual-sided memory module with channels aligned in opposition

Stopping criteria for layered iterative error correction

State change in systems having devices coupled in a chained configu...

Dual-ported PCI express-based storage cartridge including single-po...

Inferring threshold voltage distributions associated with memory ce...

Apparatuses and methods including error correction code organization

Packet deconstruction/reconstruction and link-control

High density server storage unit

Systems and methods for packaging high density SSDs

Methods for controlling host memory access with memory devices and...

Inferring threshold voltage distributions associated with memory ce...

Power consumption control

Multiple engine sequencer

Memory devices and systems configured to adjust a size of an ECC co...

Apparatus and method for accessing a non-volatile memory blade usin...

Memory apparatus, systems, and methods

Chained bus method

Systems and methods for securing high density SSDs

Configuring and reconfiguring blocks of memory cells to store user...

Host controller

High capacity storage unit

Memory cell coupling compensation

Patents Applicationslast 30 patents

LAYOUT FOR DUAL IN-LINE MEMORY TO SUPPORT 128-BYTE CACHE LINE PROCE...

STOPPING CRITERIA FOR LAYERED ITERATIVE ERROR CORRECTION

MEMORY DEVICES HAVING DIFFERENTLY CONFIGURED BLOCKS OF MEMORY CELLS

MEMORY DEVICES HAVING DIFFERENTLY CONFIGURED BLOCKS OF MEMORY CELLS

DUAL-SIDED MEMORY MODULE WITH CHANNELS ALIGNED IN OPPOSITION

STOPPING CRITERIA FOR LAYERED ITERATIVE ERROR CORRECTION

STATE CHANGE IN SYSTEMS HAVING DEVICES COUPLED IN A CHAINED CONFIGU...

DUAL-SIDED MEMORY MODULE WITH CHANNELS ALIGNED IN OPPOSITION

DUAL-PORTED PCI EXPRESS-BASED STORAGE CARTRIDGE INCLUDING SINGLE-PO...

INFERRING THRESHOLD VOLTAGE DISTRIBUTIONS ASSOCIATED WITH MEMORY CE...

CHAINED BUS METHOD

MEMORY DEVICES HAVING DIFFERENTLY CONFIGURED BLOCKS OF MEMORY CELLS

POWER CONSUMPTION CONTROL

APPARATUSES AND METHODS INCLUDING ERROR CORRECTION CODE ORGANIZATION

APPARATUS AND METHOD FOR ACCESSING A NON-VOLATILE MEMORY BLADE USIN...

INFERRING THRESHOLD VOLTAGE DISTRIBUTIONS ASSOCIATED WITH MEMORY CE...

SYSTEMS AND METHODS FOR PACKAGING HIGH DENSITY SSDS

MEMORY CELL COUPLING COMPENSATION

HIGH DENSITY SERVER STORAGE UNIT

DYNAMIC PROGRAM WINDOW DETERMINATION IN A MEMORY DEVICE

STATE CHANGE IN SYSTEMS HAVING DEVICES COUPLED IN A CHAINED CONFIGU...

APPARATUS AND METHOD FOR ROUTING INFORMATION IN A NON-VOLATILE MEMO...

HOST CONTROLLER

DYNAMIC PROGRAM WINDOW DETERMINATION IN A MEMORY DEVICE

STOPPING CRITERIA FOR LAYERED ITERATIVE ERROR CORRECTION

MEMORY APPARATUS, SYSTEMS, AND METHODS

STATE CHANGE IN SYSTEMS HAVING DEVICES COUPLED IN A CHAINED CONFIGU...

DETERMINING AND USING SOFT DATA IN MEMORY DEVICES AND SYSTEMS

THRESHOLD VOLTAGE COMPENSATION IN A MEMORY

MEMORY CONTROLLER SUPPORTING RATE-COMPATIBLE PUNCTURED CODES