William J. Butera

Person

Cambridge, MA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Layered super-reticle computing : architectures and methods
- Patent number 11,656,662
- Issue date May 23, 2023
- Intel Corporation
- Simon C. Steely
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Signal pathways in multi-tile processors
- Patent number 11,269,805
- Issue date Mar 8, 2022
- Intel Corporation
- William J. Butera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layered super-reticle computing : architectures and methods
- Patent number 10,963,022
- Issue date Mar 30, 2021
- Intel Corporation
- Simon C. Steely
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Switchable topology processor tile and computing machine
- Patent number 10,891,254
- Issue date Jan 12, 2021
- Intel Corporation
- William J. Butera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layered super-reticle computing: architectures and methods
- Patent number 10,691,182
- Issue date Jun 23, 2020
- Intel Corporation
- Simon C. Steely
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
REGISTER FILE VIRTUALIZATION : APPLICATIONS AND METHODS
- Publication number 20230195388
- Publication date Jun 22, 2023
- Intel Corporation
- William Butera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LAYERED SUPER-RETICLE COMPUTING : ARCHITECTURES AND METHODS
- Publication number 20210255674
- Publication date Aug 19, 2021
- Intel Corporation
- Simon C. Steely
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LAYERED SUPER-RETICLE COMPUTING : ARCHITECTURES AND METHODS
- Publication number 20200371566
- Publication date Nov 26, 2020
- Intel Corporation
- Simon C. Steely
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LAYERED SUPER-RETICLE COMPUTING : ARCHITECTURES AND METHODS
- Publication number 20190354146
- Publication date Nov 21, 2019
- Intel Corporation
- Simon C. Steely
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SIGNAL PATHWAYS IN MULTI-TILE PROCESSORS
- Publication number 20190042534
- Publication date Feb 7, 2019
- Intel Corporation
- William J. Butera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SWITCHABLE TOPOLOGY MACHINE
- Publication number 20180113838
- Publication date Apr 26, 2018
- Intel Corporation
- William J. Butera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and Apparatus for Controlling a Plant Using Feedback Signals
- Publication number 20110238189
- Publication date Sep 29, 2011
- William J. Butera
- G05 - CONTROLLING REGULATING

William J. Butera

Person

Patents Grantslast 30 patents

Layered super-reticle computing : architectures and methods

Signal pathways in multi-tile processors

Layered super-reticle computing : architectures and methods

Switchable topology processor tile and computing machine

Layered super-reticle computing: architectures and methods

Patents Applicationslast 30 patents

REGISTER FILE VIRTUALIZATION : APPLICATIONS AND METHODS

LAYERED SUPER-RETICLE COMPUTING : ARCHITECTURES AND METHODS

LAYERED SUPER-RETICLE COMPUTING : ARCHITECTURES AND METHODS

LAYERED SUPER-RETICLE COMPUTING : ARCHITECTURES AND METHODS

SIGNAL PATHWAYS IN MULTI-TILE PROCESSORS

SWITCHABLE TOPOLOGY MACHINE

Method and Apparatus for Controlling a Plant Using Feedback Signals