William John Livingstone

Person

Cambridge, VT, US

People

Patents Grantslast 30 patents

Information Patent Grant
Identifying and mitigating electromigration failures in signal nets...
- Patent number 9,104,832
- Issue date Aug 11, 2015
- International Business Machines Corporation
- John E. Barwin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and computer program product for semiconductor yield esti...
- Patent number 8,136,066
- Issue date Mar 13, 2012
- International Business Machines Corporation
- Jeanne Paulette Spence Bickford
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Method to quickly estimate inductance for timing models
- Patent number 7,750,648
- Issue date Jul 6, 2010
- International Business Machines Corporation
- Eric A. Foreman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods for design rule checking with abstracted via obstructions
- Patent number 7,725,850
- Issue date May 25, 2010
- International Business Machines Corporation
- Laura R. Darden
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Forming statistical model of independently variable parameters for...
- Patent number 7,684,969
- Issue date Mar 23, 2010
- International Business Machines Corporation
- Peter A. Habitz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor yield estimation
- Patent number 7,496,874
- Issue date Feb 24, 2009
- Inetrnational Business Machines Corporation
- Jeanne Paulette Spence Bickford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for re-routing an interconnection array to improve switching...
- Patent number 7,464,359
- Issue date Dec 9, 2008
- International Business Machines Corporation
- Peter A. Habitz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of automated design and checking for ESD robustness
- Patent number 6,725,439
- Issue date Apr 20, 2004
- International Business Machines Corporation
- Philip S. Homsinger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor wiring technique for reducing electromigration
- Patent number 6,308,302
- Issue date Oct 23, 2001
- International Business Machines Corporation
- David James Hathaway
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Three dimensional track-based parasitic extraction
- Patent number 6,185,722
- Issue date Feb 6, 2001
- International Business Machines Corporation
- Laura Rohwedder Darden
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Redundant vias
- Patent number 6,026,224
- Issue date Feb 15, 2000
- International Business Machines Corporation
- Laura Rohwedder Darden
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Wiring design tool improvement for avoiding electromigration by det...
- Patent number 5,737,580
- Issue date Apr 7, 1998
- International Business Machines Corporation
- David James Hathaway
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
IDENTIFYING AND MITIGATING ELECTROMIGRATION FAILURES IN SIGNAL NETS...
- Publication number 20150205906
- Publication date Jul 23, 2015
- International Buiness Machines Corporation
- John E. Barwin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD TO QUICKLY ESTIMATE INDUCTANCE FOR TIMING MODELS
- Publication number 20090243630
- Publication date Oct 1, 2009
- International Business Machines Corporation
- Eric A. Foreman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND COMPUTER PROGRAM PRODUCT FOR SEMICONDUCTOR YIELD ESTI...
- Publication number 20090113364
- Publication date Apr 30, 2009
- International Business Machines Corporation
- Jeanne Paulette Spence Bickford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS FOR DESIGN RULE CHECKING WITH ABSTRACTED VIA OBSTRUCTIONS
- Publication number 20090037857
- Publication date Feb 5, 2009
- International Business Machines Corporation
- Laura R. Darden
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD OF REDUCING CORRECLATED COUPLING BETWEEN NETS
- Publication number 20070226673
- Publication date Sep 27, 2007
- Peter A. Habitz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
A METHOD , APPARATUS AND COMPUTER PROGRAM PRODUCT FOR SEMICONDUCTOR...
- Publication number 20070143720
- Publication date Jun 21, 2007
- Jeanne Paulette Spence Bickford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Forming statistical model of independently variable parameters for...
- Publication number 20070055487
- Publication date Mar 8, 2007
- Peter A. Habitz
- G06 - COMPUTING CALCULATING COUNTING

William John Livingstone

Person

Patents Grantslast 30 patents

Identifying and mitigating electromigration failures in signal nets...

Apparatus and computer program product for semiconductor yield esti...

Method to quickly estimate inductance for timing models

Methods for design rule checking with abstracted via obstructions

Forming statistical model of independently variable parameters for...

Semiconductor yield estimation

Method for re-routing an interconnection array to improve switching...

Method of automated design and checking for ESD robustness

Semiconductor wiring technique for reducing electromigration

Three dimensional track-based parasitic extraction

Redundant vias

Wiring design tool improvement for avoiding electromigration by det...

Patents Applicationslast 30 patents

IDENTIFYING AND MITIGATING ELECTROMIGRATION FAILURES IN SIGNAL NETS...

METHOD TO QUICKLY ESTIMATE INDUCTANCE FOR TIMING MODELS

APPARATUS AND COMPUTER PROGRAM PRODUCT FOR SEMICONDUCTOR YIELD ESTI...

METHODS FOR DESIGN RULE CHECKING WITH ABSTRACTED VIA OBSTRUCTIONS

METHOD OF REDUCING CORRECLATED COUPLING BETWEEN NETS

A METHOD , APPARATUS AND COMPUTER PROGRAM PRODUCT FOR SEMICONDUCTOR...

Forming statistical model of independently variable parameters for...