William L. Walker

Person

Fort Collins, CO, US

People

Patents Grantslast 30 patents

Information Patent Grant
Processor-guided execution of offloaded instructions using fixed fu...
- Patent number 12,153,926
- Issue date Nov 26, 2024
- Advanced Micro Devices, Inc.
- John Kalamatianos
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor-guided execution of offloaded instructions using fixed fu...
- Patent number 11,868,777
- Issue date Jan 9, 2024
- Advanced Micro Devices, Inc.
- John Kalamatianos
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Re-fetching data for L3 cache data evictions into a last-level cache
- Patent number 11,847,062
- Issue date Dec 19, 2023
- Advanced Micro Devices, Inc.
- Tarun Nakra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Ring transport employing clock wake suppression
- Patent number 11,829,196
- Issue date Nov 28, 2023
- Advanced Micro Devices, Inc.
- William L. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Retaining cache entries of a processor core during a powered-down s...
- Patent number 11,704,248
- Issue date Jul 18, 2023
- Advanced Micro Devices, Inc.
- William L. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory request throttling to constrain memory bandwidth utilization
- Patent number 11,675,703
- Issue date Jun 13, 2023
- Advanced Micro Devices, Inc.
- William L. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Rinsing cache lines from a common memory page to memory
- Patent number 11,561,906
- Issue date Jan 24, 2023
- Advanced Micro Devices, Inc.
- William L. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory request throttling to constrain memory bandwidth utilization
- Patent number 11,294,810
- Issue date Apr 5, 2022
- Advanced Micro Devices, Inc.
- William L. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Using a bloom filter to reduce the number of memory addressees trac...
- Patent number 11,226,900
- Issue date Jan 18, 2022
- Advanced Micro Devices, Inc.
- Weon Taek Na
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Probe interrupt delivery
- Patent number 11,210,246
- Issue date Dec 28, 2021
- Advanced Micro Devices, Inc.
- Vydhyanathan Kalyanasundharam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Retaining cache entries of a processor core during a powered-down s...
- Patent number 10,956,332
- Issue date Mar 23, 2021
- Advanced Micro Devices, Inc.
- William L. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Expandable buffer for memory transactions
- Patent number 10,740,029
- Issue date Aug 11, 2020
- Advanced Micro Devices, Inc.
- Gabriel H. Loh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Coherency directory entry allocation based on eviction costs
- Patent number 10,705,958
- Issue date Jul 7, 2020
- Advanced Micro Devices, Inc.
- Michael W. Boyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
I/O writes with cache steering
- Patent number 10,366,027
- Issue date Jul 30, 2019
- Advanced Micro Devices, Inc.
- Eric Christopher Morton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and method for delayed cache utilization
- Patent number 10,289,567
- Issue date May 14, 2019
- Advanced Micro Devices, Inc.
- William L. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reducing cache footprint in cache coherence directory
- Patent number 10,282,295
- Issue date May 7, 2019
- Advanced Micro Devices, Inc.
- William L. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Shadow tag memory to monitor state of cachelines at different cache...
- Patent number 10,073,776
- Issue date Sep 11, 2018
- Advanced Micro Device, Inc.
- Sriram Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and method for delayed cache utilization
- Patent number 9,946,646
- Issue date Apr 17, 2018
- Advanced Micro Devices, Inc.
- William L. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Concurrent access to cache dirty bits
- Patent number 9,940,247
- Issue date Apr 10, 2018
- Advanced Micro Devices, Inc.
- William L. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing a bus lock and translation look...
- Patent number 9,916,243
- Issue date Mar 13, 2018
- Advanced Micro Devices, Inc.
- William L. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic multithreaded cache allocation
- Patent number 9,864,681
- Issue date Jan 9, 2018
- Advanced Micro Devices, Inc.
- William L. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic multithreaded cache allocation
- Patent number 9,529,719
- Issue date Dec 27, 2016
- Advanced Micro Devices, Inc.
- William L. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Accelerated cache rinse when preparing a power state transition
- Patent number 9,317,100
- Issue date Apr 19, 2016
- Advanced Micro Devices, Inc.
- Paul E. Kitchin
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Method and apparatus for storing a processor architectural state in...
- Patent number 9,262,322
- Issue date Feb 16, 2016
- Advanced Micro Devices, Inc.
- William L. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power management of multiple compute units sharing a cache
- Patent number 9,043,628
- Issue date May 26, 2015
- Advanced Micro Devices, Inc.
- Paul Kitchin
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Method and apparatus for allocating instruction and data for a unif...
- Patent number 8,909,867
- Issue date Dec 9, 2014
- Advanced Micro Devices, Inc.
- William L. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for bypassing silicon bugs
- Patent number 8,791,713
- Issue date Jul 29, 2014
- Advanced Micro Devices, Inc.
- William L. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Simultaneous execution of two memory reference instructions with on...
- Patent number 5,829,049
- Issue date Oct 27, 1998
- Hewlett-Packard Company
- William L. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Floating point operaton throughput control
- Patent number 5,623,616
- Issue date Apr 22, 1997
- Hewlett-Packard Company
- Philip L. Vitale
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
BLOOM-BASED HIT PREDICTOR
- Publication number 20250045206
- Publication date Feb 6, 2025
- ADVANCED MICRO DEVICES, INC.
- Patrick J. Shyvers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Super-Temporal Cache Replacement Policy
- Publication number 20240411692
- Publication date Dec 12, 2024
- ADVANCED MICRO DEVICES, INC.
- Gabriel Hsiuwei Loh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
UNIFIED FLEXIBLE CACHE
- Publication number 20240220409
- Publication date Jul 4, 2024
- ADVANCED MICRO DEVICES, INC.
- Vydhyanathan Kalyanasundharam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and Apparatus for Increasing Memory Level Parallelism by Red...
- Publication number 20240202116
- Publication date Jun 20, 2024
- ADVANCED MICRO DEVICES, INC.
- Jagadish B. Kotra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSOR-GUIDED EXECUTION OF OFFLOADED INSTRUCTIONS USING FIXED FU...
- Publication number 20240126552
- Publication date Apr 18, 2024
- ADVANCED MICRO DEVICES, INC.
- JOHN KALAMATIANOS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RE-FETCHING DATA FOR L3 CACHE DATA EVICTIONS INTO A LAST-LEVEL CACHE
- Publication number 20230195643
- Publication date Jun 22, 2023
- Tarun Nakra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE RESIZING BASED ON PROCESSOR WORKLOAD
- Publication number 20230094030
- Publication date Mar 30, 2023
- Dilip Jha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY REQUEST THROTTLING TO CONSTRAIN MEMORY BANDWIDTH UTILIZATION
- Publication number 20220292019
- Publication date Sep 15, 2022
- ADVANCED MICRO DEVICES, INC.
- William L. WALKER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSOR-GUIDED EXECUTION OF OFFLOADED INSTRUCTIONS USING FIXED FU...
- Publication number 20220188117
- Publication date Jun 16, 2022
- ADVANCED MICRO DEVICES, INC.
- JOHN KALAMATIANOS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROBE INTERRUPT DELIVERY
- Publication number 20220100686
- Publication date Mar 31, 2022
- ADVANCED MICRO DEVICES, INC.
- Vydhyanathan Kalyanasundharam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
USING A BLOOM FILTER TO REDUCE THE NUMBER OF MEMORY ADDRESSEES TRAC...
- Publication number 20210232501
- Publication date Jul 29, 2021
- ADVANCED MICRO DEVICES, INC.
- Weon Taek Na
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RING TRANSPORT EMPLOYING CLOCK WAKE SUPPRESSION
- Publication number 20210116956
- Publication date Apr 22, 2021
- ADVANCED MICRO DEVICES, INC.
- William L. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RETAINING CACHE ENTRIES OF A PROCESSOR CORE DURING A POWERED-DOWN S...
- Publication number 20210056031
- Publication date Feb 25, 2021
- ADVANCED MICRO DEVICES, INC.
- William L. WALKER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COHERENCY DIRECTORY ENTRY ALLOCATION BASED ON EVICTION COSTS
- Publication number 20200065246
- Publication date Feb 27, 2020
- ADVANCED MICRO DEVICES, INC.
- Michael W. BOYER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROBE INTERRUPT DELIVERY
- Publication number 20200065275
- Publication date Feb 27, 2020
- ADVANCED MICRO DEVICES, INC.
- Vydhyanathan Kalyanasundharam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RINSING CACHE LINES FROM A COMMON MEMORY PAGE TO MEMORY
- Publication number 20190179770
- Publication date Jun 13, 2019
- ADVANCED MICRO DEVICES, INC.
- William L. WALKER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY REQUEST THROTTLING TO CONSTRAIN MEMORY BANDWIDTH UTILIZATION
- Publication number 20190179757
- Publication date Jun 13, 2019
- ADVANCED MICRO DEVICES, INC.
- William L. WALKER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUCING CACHE FOOTPRINT IN CACHE COHERENCE DIRECTORY
- Publication number 20190163632
- Publication date May 30, 2019
- ADVANCED MICRO DEVICES, INC.
- William L. WALKER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
I/O WRITES WITH CACHE STEERING
- Publication number 20190163656
- Publication date May 30, 2019
- ADVANCED MICRO DEVICES, INC.
- Eric Christopher MORTON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RETAINING CACHE ENTRIES OF A PROCESSOR CORE DURING A POWERED-DOWN S...
- Publication number 20190129853
- Publication date May 2, 2019
- Advanced Micro Devices, Inc.
- William L. WALKER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHOD FOR DELAYED CACHE UTILIZATION
- Publication number 20180217931
- Publication date Aug 2, 2018
- ADVANCED MICRO DEVICES, INC.
- William L. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHOD FOR DELAYED CACHE UTILIZATION
- Publication number 20180067856
- Publication date Mar 8, 2018
- Advanced Micro Devices, Inc.
- William L. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SHADOW TAG MEMORY TO MONITOR STATE OF CACHELINES AT DIFFERENT CACHE...
- Publication number 20170371786
- Publication date Dec 28, 2017
- Advanced Micro Devices, Inc.
- Sriram Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SETTING CACHE ENTRY AGE BASED ON HINTS FROM ANOTHER CACHE LEVEL
- Publication number 20170357585
- Publication date Dec 14, 2017
- Advanced Micro Devices, Inc.
- Paul James Moyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Dynamic Multithreaded Cache Allocation
- Publication number 20170083435
- Publication date Mar 23, 2017
- Advanced Micro Devices, Inc.
- William L. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR PERFORMING A BUS LOCK AND TRANSLATION LOOK...
- Publication number 20150120976
- Publication date Apr 30, 2015
- Advanced Micro Devices, Inc.
- William L. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STORING NON-TEMPORAL CACHE DATA
- Publication number 20150095586
- Publication date Apr 2, 2015
- ADVANCED MICRO DEVICES , INC.
- William L Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR STORING A PROCESSOR ARCHITECTURAL STATE IN...
- Publication number 20150081980
- Publication date Mar 19, 2015
- Advanced Micro Devices, Inc.
- William L. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ACCELERATED CACHE RINSE WHEN PREPARING A POWER STATE TRANSITION
- Publication number 20140195832
- Publication date Jul 10, 2014
- Advanced Micro Devices, Inc.
- Paul E. Kitchin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ATOMIC TIME COUNTER SYNCHRONIZATION
- Publication number 20140189265
- Publication date Jul 3, 2014
- Advanced Micro Devices, Inc.
- Paul Kitchin
- G06 - COMPUTING CALCULATING COUNTING

William L. Walker

Person

Patents Grantslast 30 patents

Processor-guided execution of offloaded instructions using fixed fu...

Processor-guided execution of offloaded instructions using fixed fu...

Re-fetching data for L3 cache data evictions into a last-level cache

Ring transport employing clock wake suppression

Retaining cache entries of a processor core during a powered-down s...

Memory request throttling to constrain memory bandwidth utilization

Rinsing cache lines from a common memory page to memory

Memory request throttling to constrain memory bandwidth utilization

Using a bloom filter to reduce the number of memory addressees trac...

Probe interrupt delivery

Retaining cache entries of a processor core during a powered-down s...

Expandable buffer for memory transactions

Coherency directory entry allocation based on eviction costs

I/O writes with cache steering

Systems and method for delayed cache utilization

Reducing cache footprint in cache coherence directory

Shadow tag memory to monitor state of cachelines at different cache...

Systems and method for delayed cache utilization

Concurrent access to cache dirty bits

Method and apparatus for performing a bus lock and translation look...

Dynamic multithreaded cache allocation

Dynamic multithreaded cache allocation

Accelerated cache rinse when preparing a power state transition

Method and apparatus for storing a processor architectural state in...

Power management of multiple compute units sharing a cache

Method and apparatus for allocating instruction and data for a unif...

Method and apparatus for bypassing silicon bugs

Simultaneous execution of two memory reference instructions with on...

Floating point operaton throughput control

Patents Applicationslast 30 patents

BLOOM-BASED HIT PREDICTOR

Super-Temporal Cache Replacement Policy

UNIFIED FLEXIBLE CACHE

Method and Apparatus for Increasing Memory Level Parallelism by Red...

PROCESSOR-GUIDED EXECUTION OF OFFLOADED INSTRUCTIONS USING FIXED FU...

RE-FETCHING DATA FOR L3 CACHE DATA EVICTIONS INTO A LAST-LEVEL CACHE

CACHE RESIZING BASED ON PROCESSOR WORKLOAD

MEMORY REQUEST THROTTLING TO CONSTRAIN MEMORY BANDWIDTH UTILIZATION

PROCESSOR-GUIDED EXECUTION OF OFFLOADED INSTRUCTIONS USING FIXED FU...

PROBE INTERRUPT DELIVERY

USING A BLOOM FILTER TO REDUCE THE NUMBER OF MEMORY ADDRESSEES TRAC...

RING TRANSPORT EMPLOYING CLOCK WAKE SUPPRESSION

RETAINING CACHE ENTRIES OF A PROCESSOR CORE DURING A POWERED-DOWN S...

COHERENCY DIRECTORY ENTRY ALLOCATION BASED ON EVICTION COSTS

PROBE INTERRUPT DELIVERY

RINSING CACHE LINES FROM A COMMON MEMORY PAGE TO MEMORY

MEMORY REQUEST THROTTLING TO CONSTRAIN MEMORY BANDWIDTH UTILIZATION

REDUCING CACHE FOOTPRINT IN CACHE COHERENCE DIRECTORY

I/O WRITES WITH CACHE STEERING

RETAINING CACHE ENTRIES OF A PROCESSOR CORE DURING A POWERED-DOWN S...

SYSTEMS AND METHOD FOR DELAYED CACHE UTILIZATION

SYSTEMS AND METHOD FOR DELAYED CACHE UTILIZATION

SHADOW TAG MEMORY TO MONITOR STATE OF CACHELINES AT DIFFERENT CACHE...

SETTING CACHE ENTRY AGE BASED ON HINTS FROM ANOTHER CACHE LEVEL

Dynamic Multithreaded Cache Allocation

METHOD AND APPARATUS FOR PERFORMING A BUS LOCK AND TRANSLATION LOOK...

STORING NON-TEMPORAL CACHE DATA

METHOD AND APPARATUS FOR STORING A PROCESSOR ARCHITECTURAL STATE IN...

ACCELERATED CACHE RINSE WHEN PREPARING A POWER STATE TRANSITION

ATOMIC TIME COUNTER SYNCHRONIZATION