William O'Leary

Person

Plano, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Multiple data channel memory module architecture
- Patent number 11,550,719
- Issue date Jan 10, 2023
- Micron Technology, Inc.
- Tony M. Brewer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple data channel memory module architecture
- Patent number 10,949,347
- Issue date Mar 16, 2021
- Micron Technology, Inc.
- Tony M. Brewer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple data channel memory module architecture
- Patent number 10,061,699
- Issue date Aug 28, 2018
- Micron Technology, Inc.
- Tony M. Brewer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple data channel memory module architecture
- Patent number 9,824,010
- Issue date Nov 21, 2017
- Micron Technology, Inc.
- Tony M. Brewer
- G11 - INFORMATION STORAGE
Information Patent Grant
Multiple data channel memory module architecture
- Patent number 9,449,659
- Issue date Sep 20, 2016
- Micron Technology, Inc.
- Tony M. Brewer
- G11 - INFORMATION STORAGE
Information Patent Grant
Multiple data channel memory module architecture
- Patent number 9,015,399
- Issue date Apr 21, 2015
- Convey Computer
- Tony M. Brewer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Phase comparator for a phase locked loop
- Patent number 6,950,957
- Issue date Sep 27, 2005
- ADC Telecommunications, Inc.
- William O'Leary
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Timing and synchronization for an IP router using an optical switch
- Patent number 6,711,357
- Issue date Mar 23, 2004
- Chiaro Networks Ltd.
- Tony Brewer
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Direct digital synthesizer phase locked loop
- Patent number 6,664,827
- Issue date Dec 16, 2003
- ADC Telecommunications, Inc.
- William O'Leary
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Patents Applicationslast 30 patents

Information Patent Application
MULTIPLE DATA CHANNEL MEMORY MODULE ARCHITECTURE
- Publication number 20210182195
- Publication date Jun 17, 2021
- Micron Technology, Inc.
- TONY M. BREWER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLE DATA CHANNEL MEMORY MODULE ARCHITECTURE
- Publication number 20180322054
- Publication date Nov 8, 2018
- Micron Technology, Inc.
- TONY M. BREWER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLE DATA CHANNEL MEMORY MODULE ARCHITECTURE
- Publication number 20180060234
- Publication date Mar 1, 2018
- Micron Technology, Inc.
- TONY M. BREWER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLE DATA CHANNEL MEMORY MODULE ARCHITECTURE
- Publication number 20160371185
- Publication date Dec 22, 2016
- Micron Technology, Inc.
- TONY M. BREWER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLE DATA CHANNEL MEMORY MODULE ARCHITECTURE
- Publication number 20150206561
- Publication date Jul 23, 2015
- Convey Computer
- Tony M. Brewer
- G11 - INFORMATION STORAGE
Information Patent Application
MULTIPLE DATA CHANNEL MEMORY MODULE ARCHITECTURE
- Publication number 20100036997
- Publication date Feb 11, 2010
- Convey Computer
- Tony M. Brewer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Direct digital synthesizer phase locked loop
- Publication number 20020180498
- Publication date Dec 5, 2002
- William O'Leary
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

William O'Leary

Person

Patents Grantslast 30 patents

Multiple data channel memory module architecture

Multiple data channel memory module architecture

Multiple data channel memory module architecture

Multiple data channel memory module architecture

Multiple data channel memory module architecture

Multiple data channel memory module architecture

Phase comparator for a phase locked loop

Timing and synchronization for an IP router using an optical switch

Direct digital synthesizer phase locked loop

Patents Applicationslast 30 patents

MULTIPLE DATA CHANNEL MEMORY MODULE ARCHITECTURE

MULTIPLE DATA CHANNEL MEMORY MODULE ARCHITECTURE

MULTIPLE DATA CHANNEL MEMORY MODULE ARCHITECTURE

MULTIPLE DATA CHANNEL MEMORY MODULE ARCHITECTURE

MULTIPLE DATA CHANNEL MEMORY MODULE ARCHITECTURE

MULTIPLE DATA CHANNEL MEMORY MODULE ARCHITECTURE

Direct digital synthesizer phase locked loop