William P. Hovis

Person

Rochester, MN, US

People

Patents Grantslast 30 patents

Information Patent Grant
System and memory controller for interruptible memory refresh
- Patent number 10,096,353
- Issue date Oct 9, 2018
- International Business Machines Corporation
- Edgar R. Cordero
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device for interruptible memory refresh
- Patent number 9,972,376
- Issue date May 15, 2018
- International Business Machines Corporation
- Edgar R. Cordero
- G11 - INFORMATION STORAGE
Information Patent Grant
Donor cores to improve integrated circuit yield
- Patent number 9,612,988
- Issue date Apr 4, 2017
- International Business Machines Corporation
- Gerald K. Bartley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple active vertically aligned cores for three-dimensional chip...
- Patent number 9,568,940
- Issue date Feb 14, 2017
- International Business Machines Corporation
- Gerald K. Bartley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit design for balanced logic stress
- Patent number 9,383,767
- Issue date Jul 5, 2016
- International Business Machines Corporation
- Nathaniel R. Chadwick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Intelligent chip placement within a three-dimensional chip stack
- Patent number 9,312,199
- Issue date Apr 12, 2016
- International Business Machines Corporation
- Gerald K. Bartley
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multiple active vertically aligned cores for three-dimensional chip...
- Patent number 9,310,827
- Issue date Apr 12, 2016
- International Business Machines Corporation
- Gerald K. Bartley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Intelligent chip placement within a three-dimensional chip stack
- Patent number 9,281,261
- Issue date Mar 8, 2016
- International Business Machines Corporation
- Gerald K. Bartley
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Circuit design for balanced logic stress
- Patent number 9,250,645
- Issue date Feb 2, 2016
- International Business Machines Corporation
- Nathaniel R. Chadwick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interconnect solder bumps for die testing
- Patent number 9,207,275
- Issue date Dec 8, 2015
- International Business Machines Corporation
- Gerald K. Bartley
- G01 - MEASURING TESTING
Information Patent Grant
Determining chip burn-in workload using emulated application condition
- Patent number 8,943,458
- Issue date Jan 27, 2015
- International Business Machines Corporation
- Nathaniel R. Chadwick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Setting a reference voltage in a memory controller trained to a mem...
- Patent number 8,902,681
- Issue date Dec 2, 2014
- International Business Machines Corporation
- Benjamin A. Fox
- G11 - INFORMATION STORAGE
Information Patent Grant
Training a memory controller and a memory device using multiple rea...
- Patent number 8,681,571
- Issue date Mar 25, 2014
- International Business Machines Corporation
- Benjamin A. Fox
- G11 - INFORMATION STORAGE
Information Patent Grant
Sorting movable memory hierarchies in a computer system
- Patent number 8,639,879
- Issue date Jan 28, 2014
- International Business Machines Corporation
- Gerald K. Bartley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Setting a reference voltage in a memory controller trained to a mem...
- Patent number 8,289,784
- Issue date Oct 16, 2012
- International Business Machines Corporation
- Benjamin A. Fox
- G11 - INFORMATION STORAGE
Information Patent Grant
Structure for multi-level memory architecture with data prioritization
- Patent number 8,255,628
- Issue date Aug 28, 2012
- International Business Machines Corporation
- Gerald K. Bartley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Setting controller termination in a memory controller and memory de...
- Patent number 8,111,564
- Issue date Feb 7, 2012
- International Business Machines Corporation
- Benjamin A Fox
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Digital data architecture employing redundant links in a daisy chai...
- Patent number 8,108,647
- Issue date Jan 31, 2012
- International Business Machines Corporation
- Gerald Keith Bartley
- G11 - INFORMATION STORAGE
Information Patent Grant
Setting controller VREF in a memory controller and memory device in...
- Patent number 8,102,724
- Issue date Jan 24, 2012
- International Business Machines Corporation
- Benjamin A Fox
- G11 - INFORMATION STORAGE
Information Patent Grant
Setting memory controller driver to memory device termination value...
- Patent number 7,990,768
- Issue date Aug 2, 2011
- International Business Machines Corporation
- Benjamin A Fox
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Setting memory device termination in a memory device and memory con...
- Patent number 7,978,538
- Issue date Jul 12, 2011
- International Business Machines Corporation
- Benjamin A Fox
- G11 - INFORMATION STORAGE
Information Patent Grant
Setting memory device VREF in a memory controller and memory device...
- Patent number 7,974,141
- Issue date Jul 5, 2011
- International Business Machines Corporation
- Benjamin A Fox
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor scheme for reduced circuit area in a simplified process
- Patent number 7,935,629
- Issue date May 3, 2011
- International Business Machines Corporation
- Todd Alan Christensen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory controller and method for optimized read/modify/write perfor...
- Patent number 7,908,443
- Issue date Mar 15, 2011
- International Business Machines Corporation
- Philip Rogers Hillier, III
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for implementing redundant memory access using...
- Patent number 7,882,479
- Issue date Feb 1, 2011
- International Business Machines Corporation
- Gerald Keith Bartley
- G11 - INFORMATION STORAGE
Information Patent Grant
Bulk FinFET device
- Patent number 7,863,122
- Issue date Jan 4, 2011
- International Business Machines Corporation
- Roger Allen Booth, Jr.
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Calibration of memory driver with offset in a memory controller and...
- Patent number 7,848,175
- Issue date Dec 7, 2010
- International Business Machines Corporation
- Benjamin A Fox
- G11 - INFORMATION STORAGE
Information Patent Grant
Diagnostic interface architecture for memory device
- Patent number 7,802,158
- Issue date Sep 21, 2010
- International Business Machines Corporation
- John Michael Borkenhagen
- G11 - INFORMATION STORAGE
Information Patent Grant
Design structure of implementing power savings during addressing of...
- Patent number 7,791,978
- Issue date Sep 7, 2010
- International Business Machines Corporation
- Gerald K. Bartley
- G11 - INFORMATION STORAGE
Information Patent Grant
Handling DMA operations during a page copy
- Patent number 7,783,793
- Issue date Aug 24, 2010
- International Business Machines Corporation
- Gerald Keith Bartley
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
CIRCUIT DESIGN FOR BALANCED LOGIC STRESS
- Publication number 20150253807
- Publication date Sep 10, 2015
- International Business Machines Corporation
- Nathaniel R. Chadwick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CIRCUIT DESIGN FOR BALANCED LOGIC STRESS
- Publication number 20150253808
- Publication date Sep 10, 2015
- International Business Machines Corporation
- Nathaniel R. Chadwick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTELLIGENT CHIP PLACEMENT WITHIN A THREE-DIMENSIONAL CHIP STACK
- Publication number 20150162250
- Publication date Jun 11, 2015
- International Business Machines Corporation
- Gerald K. Bartley
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTIPLE ACTIVE VERTICALLY ALIGNED CORES FOR THREE-DIMENSIONAL CHIP...
- Publication number 20150162311
- Publication date Jun 11, 2015
- International Business Machines Corporation
- Gerald K. Bartley
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTELLIGENT CHIP PLACEMENT WITHIN A THREE-DIMENSIONAL CHIP STACK
- Publication number 20150162259
- Publication date Jun 11, 2015
- International Business Machines Corporation
- Gerald K. Bartley
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTIPLE ACTIVE VERTICALLY ALIGNED CORES FOR THREE-DIMENSIONAL CHIP...
- Publication number 20150160685
- Publication date Jun 11, 2015
- International Business Machines Corporation
- Gerald K. Bartley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICE FOR INTERRUPTIBLE MEMORY REFRESH
- Publication number 20150127899
- Publication date May 7, 2015
- International Business Machines Corporation
- Edgar R. Cordero
- G11 - INFORMATION STORAGE
Information Patent Application
SYSTEM AND MEMORY CONTROLLER FOR INTERRUPTIBLE MEMORY REFRESH
- Publication number 20150127898
- Publication date May 7, 2015
- International Business Machines Corporation
- Edgar R. Cordero
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD FOR RELATING TEST TIME AND ESCAPE RATE FOR MULTIVARIATE ISSUE
- Publication number 20150051869
- Publication date Feb 19, 2015
- International Business Machines Corporation
- Jennifer E. Appleyard
- G01 - MEASURING TESTING
Information Patent Application
DONOR CORES TO IMPROVE INTEGRATED CIRCUIT YIELD
- Publication number 20150032933
- Publication date Jan 29, 2015
- International Business Machines Corporation
- Gerald K. Bartley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERCONNECT SOLDER BUMPS FOR DIE TESTING
- Publication number 20140167808
- Publication date Jun 19, 2014
- International Business Machines Corporation
- Gerald K. Bartley
- G01 - MEASURING TESTING
Information Patent Application
Setting a Reference Voltage in a Memory Controller Trained to a Mem...
- Publication number 20120224436
- Publication date Sep 6, 2012
- Benjamin A. Fox
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Setting a Reference Voltage in a Memory Controller Trained to a Mem...
- Publication number 20110307717
- Publication date Dec 15, 2011
- International Business Machines Corporation
- Benjamin A. Fox
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Training a Memory Controller and a Memory Device Using Multiple Rea...
- Publication number 20110307671
- Publication date Dec 15, 2011
- International Business Machines Corporation
- Benjamin A. Fox
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SORTING MOVABLE MEMORY HIERARCHIES IN A COMPUTER SYSTEM
- Publication number 20110238879
- Publication date Sep 29, 2011
- International Business Machines Corporation
- Gerald K. Bartley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Setting Memory Device Termination in a Memory Device and Memory Con...
- Publication number 20100188917
- Publication date Jul 29, 2010
- International Business Machines Corporation
- Benjamin A. Fox
- G11 - INFORMATION STORAGE
Information Patent Application
Calibration of Memory Driver With Offset in a Memory Controller and...
- Publication number 20100188919
- Publication date Jul 29, 2010
- International Business Machines Corporation
- Benjamin A. Fox
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Digital Data Architecture Employing Redundant Links in a Daisy Chai...
- Publication number 20100191894
- Publication date Jul 29, 2010
- International Business Machines Corporation
- Gerald Keith Bartley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Setting Controller Termination in a Memory Controller and Memory De...
- Publication number 20100192000
- Publication date Jul 29, 2010
- International Business Machines Corporation
- Benjamin A. Fox
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Setting Memory Controller Driver to Memory Device Termination Value...
- Publication number 20100188916
- Publication date Jul 29, 2010
- International Business Machines Corporation
- Benjamin A. Fox
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Setting Memory Device VREF in a Memory Controller and Memory Device...
- Publication number 20100188908
- Publication date Jul 29, 2010
- International Business Machines Corporation
- Benjamin A. Fox
- G11 - INFORMATION STORAGE
Information Patent Application
Setting Controller VREF in a Memory Controller and Memory Device In...
- Publication number 20100188918
- Publication date Jul 29, 2010
- International Business Machines Corporation
- Benjamin A. Fox
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Implementing Cache Coherency and Reduced Latency Using Multiple Con...
- Publication number 20090300291
- Publication date Dec 3, 2009
- Gerald Keith Bartley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Implementing Redundant Memory Access Using Multiple Controllers for...
- Publication number 20090300411
- Publication date Dec 3, 2009
- Gerald Keith Bartley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Design Structure Of Implementing Power Savings During Addressing Of...
- Publication number 20090196118
- Publication date Aug 6, 2009
- International Business Machines Corporation
- Gerald K. Bartley
- G11 - INFORMATION STORAGE
Information Patent Application
DIAGNOSTIC INTERFACE ARCHITECTURE FOR MEMORY DEVICE
- Publication number 20090183039
- Publication date Jul 16, 2009
- International Business Machines Corporation
- John Michael Borkenhagen
- G11 - INFORMATION STORAGE
Information Patent Application
DYNAMIC RECONFIGURATION OF SOLID STATE MEMORY DEVICE TO REPLICATE...
- Publication number 20090073739
- Publication date Mar 19, 2009
- International Business Machines Corporation
- Gerald Keith Bartley
- G11 - INFORMATION STORAGE
Information Patent Application
Method and Data Receiver Apparatus for Implementing Memory Read Dat...
- Publication number 20090046813
- Publication date Feb 19, 2009
- International Business Machines Corporation
- William Paul Hovis
- G11 - INFORMATION STORAGE
Information Patent Application
Method and Data Receiver Apparatus for Implementing Memory Read Dat...
- Publication number 20090046812
- Publication date Feb 19, 2009
- William Paul Hovis
- G11 - INFORMATION STORAGE
Information Patent Application
Spider Web Interconnect Topology Utilizing Multiple Port Connection
- Publication number 20090031067
- Publication date Jan 29, 2009
- Gerald K. Bartley
- G06 - COMPUTING CALCULATING COUNTING

William P. Hovis

Person

Patents Grantslast 30 patents

System and memory controller for interruptible memory refresh

Memory device for interruptible memory refresh

Donor cores to improve integrated circuit yield

Multiple active vertically aligned cores for three-dimensional chip...

Circuit design for balanced logic stress

Intelligent chip placement within a three-dimensional chip stack

Multiple active vertically aligned cores for three-dimensional chip...

Intelligent chip placement within a three-dimensional chip stack

Circuit design for balanced logic stress

Interconnect solder bumps for die testing

Determining chip burn-in workload using emulated application condition

Setting a reference voltage in a memory controller trained to a mem...

Training a memory controller and a memory device using multiple rea...

Sorting movable memory hierarchies in a computer system

Setting a reference voltage in a memory controller trained to a mem...

Structure for multi-level memory architecture with data prioritization

Setting controller termination in a memory controller and memory de...

Digital data architecture employing redundant links in a daisy chai...

Setting controller VREF in a memory controller and memory device in...

Setting memory controller driver to memory device termination value...

Setting memory device termination in a memory device and memory con...

Setting memory device VREF in a memory controller and memory device...

Semiconductor scheme for reduced circuit area in a simplified process

Memory controller and method for optimized read/modify/write perfor...

Method and apparatus for implementing redundant memory access using...

Bulk FinFET device

Calibration of memory driver with offset in a memory controller and...

Diagnostic interface architecture for memory device

Design structure of implementing power savings during addressing of...

Handling DMA operations during a page copy

Patents Applicationslast 30 patents

CIRCUIT DESIGN FOR BALANCED LOGIC STRESS

CIRCUIT DESIGN FOR BALANCED LOGIC STRESS

INTELLIGENT CHIP PLACEMENT WITHIN A THREE-DIMENSIONAL CHIP STACK

MULTIPLE ACTIVE VERTICALLY ALIGNED CORES FOR THREE-DIMENSIONAL CHIP...

INTELLIGENT CHIP PLACEMENT WITHIN A THREE-DIMENSIONAL CHIP STACK

MULTIPLE ACTIVE VERTICALLY ALIGNED CORES FOR THREE-DIMENSIONAL CHIP...

MEMORY DEVICE FOR INTERRUPTIBLE MEMORY REFRESH

SYSTEM AND MEMORY CONTROLLER FOR INTERRUPTIBLE MEMORY REFRESH

METHOD FOR RELATING TEST TIME AND ESCAPE RATE FOR MULTIVARIATE ISSUE

DONOR CORES TO IMPROVE INTEGRATED CIRCUIT YIELD

INTERCONNECT SOLDER BUMPS FOR DIE TESTING

Setting a Reference Voltage in a Memory Controller Trained to a Mem...

Setting a Reference Voltage in a Memory Controller Trained to a Mem...

Training a Memory Controller and a Memory Device Using Multiple Rea...

SORTING MOVABLE MEMORY HIERARCHIES IN A COMPUTER SYSTEM

Setting Memory Device Termination in a Memory Device and Memory Con...

Calibration of Memory Driver With Offset in a Memory Controller and...

Digital Data Architecture Employing Redundant Links in a Daisy Chai...

Setting Controller Termination in a Memory Controller and Memory De...

Setting Memory Controller Driver to Memory Device Termination Value...

Setting Memory Device VREF in a Memory Controller and Memory Device...

Setting Controller VREF in a Memory Controller and Memory Device In...

Implementing Cache Coherency and Reduced Latency Using Multiple Con...

Implementing Redundant Memory Access Using Multiple Controllers for...

Design Structure Of Implementing Power Savings During Addressing Of...

DIAGNOSTIC INTERFACE ARCHITECTURE FOR MEMORY DEVICE

DYNAMIC RECONFIGURATION OF SOLID STATE MEMORY DEVICE TO REPLICATE...

Method and Data Receiver Apparatus for Implementing Memory Read Dat...

Method and Data Receiver Apparatus for Implementing Memory Read Dat...

Spider Web Interconnect Topology Utilizing Multiple Port Connection