William R. Halleck

Person

Lancaster, MA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Multiple dies hardware processors and methods
- Patent number 11,899,615
- Issue date Feb 13, 2024
- Intel Corporation
- Nevine Nassif
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple dies hardware processors and methods
- Patent number 11,586,579
- Issue date Feb 21, 2023
- Intel Corporation
- Nevine Nassif
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bimodal PHY for low latency in high speed interconnects
- Patent number 11,354,264
- Issue date Jun 7, 2022
- Intel Corporation
- Venkatraman Iyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple dies hardware processors and methods
- Patent number 11,294,852
- Issue date Apr 5, 2022
- Intel Corporation
- Nevine Nassif
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bimodal PHY for low latency in high speed interconnects
- Patent number 10,963,415
- Issue date Mar 30, 2021
- Intel Corporation
- Venkatraman Iyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High speed interconnect with channel extension
- Patent number 10,931,329
- Issue date Feb 23, 2021
- Intel Corporation
- Rahul R. Shah
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple dies hardware processors and methods
- Patent number 10,795,853
- Issue date Oct 6, 2020
- Intel Corporation
- Nevine Nassif
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bimodal phy for low latency in high speed interconnects
- Patent number 10,599,602
- Issue date Mar 24, 2020
- Intel Corporation
- Venkatraman Iyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bimodal PHY for low latency in high speed interconnects
- Patent number 10,372,657
- Issue date Aug 6, 2019
- Intel Corporation
- Venkatraman Iyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High performance interconnect link state transitions
- Patent number 10,324,882
- Issue date Jun 18, 2019
- Intel Corporation
- William R. Halleck
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Link-physical layer interface adapter
- Patent number 10,152,446
- Issue date Dec 11, 2018
- Intel Corporation
- Venkatraman Iyer
- G11 - INFORMATION STORAGE
Information Patent Grant
High performance interconnect
- Patent number 10,025,746
- Issue date Jul 17, 2018
- Intel Corporation
- William R. Halleck
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High performance interconnect link state transitions
- Patent number 9,910,809
- Issue date Mar 6, 2018
- Intel Corporation
- William R. Halleck
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Task scheduling to devices with same connection address
- Patent number 8,135,869
- Issue date Mar 13, 2012
- Intel Corporation
- Naichih Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hardware assisted receive channel frame handling via data offset co...
- Patent number 7,797,463
- Issue date Sep 14, 2010
- Intel Corporation
- William Halleck
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Task context direct indexing in a protocol engine
- Patent number 7,676,604
- Issue date Mar 9, 2010
- Intel Corporation
- William Halleck
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
DMA descriptor management mechanism
- Patent number 7,664,889
- Issue date Feb 16, 2010
- Intel Corporation
- Kiran Vemula
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Parallel processing of frame based data transfers
- Patent number 7,506,080
- Issue date Mar 17, 2009
- Inter Corporation
- Victor Lau
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
DMA completion processing mechanism
- Patent number 7,415,549
- Issue date Aug 19, 2008
- Intel Corporation
- Kiran Vemula
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Wide-port context cache apparatus, systems, and methods
- Patent number 7,376,789
- Issue date May 20, 2008
- Intel Corporation
- William Halleck
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
MULTIPLE DIES HARDWARE PROCESSORS AND METHODS
- Publication number 20230169032
- Publication date Jun 1, 2023
- Intel Corporation
- NEVINE NASSIF
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLE DIES HARDWARE PROCESSORS AND METHODS
- Publication number 20220050805
- Publication date Feb 17, 2022
- Intel Corporation
- NEVINE NASSIF
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BIMODAL PHY FOR LOW LATENCY IN HIGH SPEED INTERCONNECTS
- Publication number 20210182231
- Publication date Jun 17, 2021
- Intel Corporation
- Venkatraman Iyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLE DIES HARDWARE PROCESSORS AND METHODS
- Publication number 20200334196
- Publication date Oct 22, 2020
- Intel Corporation
- NEVINE NASSIF
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BIMODAL PHY FOR LOW LATENCY IN HIGH SPEED INTERCONNECTS
- Publication number 20200293480
- Publication date Sep 17, 2020
- Intel Corporation
- Venkatraman Iyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BIMODAL PHY FOR LOW LATENCY IN HIGH SPEED INTERCONNECTS
- Publication number 20190310959
- Publication date Oct 10, 2019
- Intel Corporation
- Venkatraman Iyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH SPEED INTERCONNECT WITH CHANNEL EXTENSION
- Publication number 20180191523
- Publication date Jul 5, 2018
- Intel Corporation
- Rahul R. Shah
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
BIMODAL PHY FOR LOW LATENCY IN HIGH SPEED INTERCONNECTS
- Publication number 20180181525
- Publication date Jun 28, 2018
- Intel Corporation
- Venkatraman Iyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLE DIES HARDWARE PROCESSORS AND METHODS
- Publication number 20180101502
- Publication date Apr 12, 2018
- NEVINE NASSIF
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LINK-PHYSICAL LAYER INTERFACE ADAPTER
- Publication number 20180095923
- Publication date Apr 5, 2018
- Intel Corporation
- Venkatraman Iyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH PERFORMANCE INTERCONNECT LINK STATE TRANSITIONS
- Publication number 20170109300
- Publication date Apr 20, 2017
- Intel Corporation
- William R. Halleck
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH PERFORMANCE INTERCONNECT
- Publication number 20160179740
- Publication date Jun 23, 2016
- Intel Corporation
- William R. Halleck
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH PERFORMANCE INTERCONNECT LINK STATE TRANSITIONS
- Publication number 20160179730
- Publication date Jun 23, 2016
- Intel Corporation
- William R. Halleck
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Task context direct indexing in a protocol engine
- Publication number 20070118835
- Publication date May 24, 2007
- William Halleck
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DMA completion processing mechanism
- Publication number 20070073921
- Publication date Mar 29, 2007
- Kiran Vemula
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DMA descriptor management mechanism
- Publication number 20070073923
- Publication date Mar 29, 2007
- Kiran Vemula
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Parallel processing of frame based data transfers
- Publication number 20070067504
- Publication date Mar 22, 2007
- Victor Lau
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Automated serial protocol initiator port transport layer retry mech...
- Publication number 20070011333
- Publication date Jan 11, 2007
- Victor Lau
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Automated serial protocol target port transport layer retry mechanism
- Publication number 20070002827
- Publication date Jan 4, 2007
- Victor Lau
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Wide-port context cache apparatus, systems, and methods
- Publication number 20070005888
- Publication date Jan 4, 2007
- Intel Corporation
- William Halleck
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Task scheduling to devices with same connection address
- Publication number 20070006235
- Publication date Jan 4, 2007
- Intel Corporation
- Naichih Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method, apparatus and system for task context cache replacement
- Publication number 20070005898
- Publication date Jan 4, 2007
- William Halleck
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Hardware assisted receive channel frame handling via data offset co...
- Publication number 20070005810
- Publication date Jan 4, 2007
- William Halleck
- G06 - COMPUTING CALCULATING COUNTING

William R. Halleck

Person

Patents Grantslast 30 patents

Multiple dies hardware processors and methods

Multiple dies hardware processors and methods

Bimodal PHY for low latency in high speed interconnects

Multiple dies hardware processors and methods

Bimodal PHY for low latency in high speed interconnects

High speed interconnect with channel extension

Multiple dies hardware processors and methods

Bimodal phy for low latency in high speed interconnects

Bimodal PHY for low latency in high speed interconnects

High performance interconnect link state transitions

Link-physical layer interface adapter

High performance interconnect

High performance interconnect link state transitions

Task scheduling to devices with same connection address

Hardware assisted receive channel frame handling via data offset co...

Task context direct indexing in a protocol engine

DMA descriptor management mechanism

Parallel processing of frame based data transfers

DMA completion processing mechanism

Wide-port context cache apparatus, systems, and methods

Patents Applicationslast 30 patents

MULTIPLE DIES HARDWARE PROCESSORS AND METHODS

MULTIPLE DIES HARDWARE PROCESSORS AND METHODS

BIMODAL PHY FOR LOW LATENCY IN HIGH SPEED INTERCONNECTS

MULTIPLE DIES HARDWARE PROCESSORS AND METHODS

BIMODAL PHY FOR LOW LATENCY IN HIGH SPEED INTERCONNECTS

BIMODAL PHY FOR LOW LATENCY IN HIGH SPEED INTERCONNECTS

HIGH SPEED INTERCONNECT WITH CHANNEL EXTENSION

BIMODAL PHY FOR LOW LATENCY IN HIGH SPEED INTERCONNECTS

MULTIPLE DIES HARDWARE PROCESSORS AND METHODS

LINK-PHYSICAL LAYER INTERFACE ADAPTER

HIGH PERFORMANCE INTERCONNECT LINK STATE TRANSITIONS

HIGH PERFORMANCE INTERCONNECT

HIGH PERFORMANCE INTERCONNECT LINK STATE TRANSITIONS

Task context direct indexing in a protocol engine

DMA completion processing mechanism

DMA descriptor management mechanism

Parallel processing of frame based data transfers

Automated serial protocol initiator port transport layer retry mech...

Automated serial protocol target port transport layer retry mechanism

Wide-port context cache apparatus, systems, and methods

Task scheduling to devices with same connection address

Method, apparatus and system for task context cache replacement

Hardware assisted receive channel frame handling via data offset co...