William Robert Reece

Person

Over, GB

People

Patents Grantslast 30 patents

Information Patent Grant
Dynamic weighting scheme for local cluster refinement
- Patent number 11,188,702
- Issue date Nov 30, 2021
- Cadence Design Systems, Inc.
- Bentian Jiang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Generate clock network using inverting integrated clock gate
- Patent number 11,163,929
- Issue date Nov 2, 2021
- Cadence Design Systems, Inc.
- William Robert Reece
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Using negative-edge integrated clock gate in clock network
- Patent number 11,132,490
- Issue date Sep 28, 2021
- Cadence Design Systems, Inc.
- Ruth Patricia Jackson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Delay dependence in physically aware cell cloning
- Patent number 10,990,721
- Issue date Apr 27, 2021
- Cadence Design Systems, Inc.
- William Robert Reece
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-dimension clock gate design in clock tree synthesis
- Patent number 10,963,618
- Issue date Mar 30, 2021
- Cadence Design Systems, Ine.
- Amin Farshidi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Modifying route topology to fix clock tree violations
- Patent number 10,963,617
- Issue date Mar 30, 2021
- Cadence Design Systems, Inc.
- Andrew Mark Chapman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Route driven placement of fan-out clock drivers
- Patent number 10,740,532
- Issue date Aug 11, 2020
- Cadence Design Systems, Inc.
- William Robert Reece
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Region aware clustering
- Patent number 10,402,522
- Issue date Sep 3, 2019
- Cadence Design Systems, Inc.
- Natarajan Viswanathan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Placement of cells in a multi-level routing tree
- Patent number 10,402,533
- Issue date Sep 3, 2019
- Cadence Design Systems, Inc.
- William Robert Reece
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Balanced scaled-load clustering
- Patent number 10,318,693
- Issue date Jun 11, 2019
- Cadence Design Systems, Inc.
- Natarajan Viswanathan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock cell library selection
- Patent number 10,198,551
- Issue date Feb 5, 2019
- Cadence Design Systems, Inc.
- Amin Farshidi
- G06 - COMPUTING CALCULATING COUNTING

William Robert Reece

Person

Patents Grantslast 30 patents

Dynamic weighting scheme for local cluster refinement

Generate clock network using inverting integrated clock gate

Using negative-edge integrated clock gate in clock network

Delay dependence in physically aware cell cloning

Multi-dimension clock gate design in clock tree synthesis

Modifying route topology to fix clock tree violations

Route driven placement of fan-out clock drivers

Region aware clustering

Placement of cells in a multi-level routing tree

Balanced scaled-load clustering

Clock cell library selection