William Schmitz

Person

Monument, CO, US

People

Patents Grantslast 30 patents

Information Patent Grant
Systems and methods for assessing timing of PCI signals
- Patent number 7,289,925
- Issue date Oct 30, 2007
- LSI Corporation
- Gordon Keith Grimes
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for analyzing data of a SAS/SATA device
- Patent number 7,120,557
- Issue date Oct 10, 2006
- LSI Logic Corporation
- William J. Schmitz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Parallel bus debugging tool
- Patent number 7,084,618
- Issue date Aug 1, 2006
- LSI Logic Corporation
- William Voorhees
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methodology to accurately test clock to signal valid and slew rates...
- Patent number 7,078,924
- Issue date Jul 18, 2006
- LSI Logic Corporation
- Keith Grimes
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for generating CRC/parity error in network env...
- Patent number 7,000,170
- Issue date Feb 14, 2006
- LSI Logic Corporation
- Mark Slutz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for analyzing data of an SPI data bus
- Patent number 6,895,365
- Issue date May 17, 2005
- LSI Logic Corporation
- William W. Voorhees
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for determining deskew margins in parallel interface receivers
- Patent number 6,892,334
- Issue date May 10, 2005
- LSI Logic Corporation
- Mark Slutz
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Testing implementation for signal characterization
- Patent number 6,822,459
- Issue date Nov 23, 2004
- LSI Logic Corporation
- Gabriel L. Romero
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
PCI bus system testing and verification apparatus and method
- Patent number 6,587,813
- Issue date Jul 1, 2003
- LSI Logic Corporation
- Jeffrey K. Whitt
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
COMPENSATING FOR JITTER DURING DDR3 MEMORY DELAY LINE TRAINING
- Publication number 20120296598
- Publication date Nov 22, 2012
- LSI Corporation
- Craig R. Chafin
- G11 - INFORMATION STORAGE
Information Patent Application
Systems and methods for analyzing data of a SAS/SATA device
- Publication number 20060259278
- Publication date Nov 16, 2006
- LSI Logic Corporation
- William J. Schmitz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Parallel bus debugging tool
- Publication number 20050134163
- Publication date Jun 23, 2005
- William Voorhees
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Systems and methods for assessing timing of PCI signals
- Publication number 20050138490
- Publication date Jun 23, 2005
- Gordon Keith Grimes
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Systems and methods for analyzing data of a SAS/SATA device
- Publication number 20040215421
- Publication date Oct 28, 2004
- William J. Schmitz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Systems and methods for analyzing data of an SPI data bus
- Publication number 20040215420
- Publication date Oct 28, 2004
- William W. Voorhees
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for generating CRC/parity error in network env...
- Publication number 20040153891
- Publication date Aug 5, 2004
- Mark Slutz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methodology to accurately test clock to signal valid and slew rates...
- Publication number 20040059975
- Publication date Mar 25, 2004
- Keith Grimes
- G01 - MEASURING TESTING
Information Patent Application
Method for determining deskew margins in parallel interface receivers
- Publication number 20040030964
- Publication date Feb 12, 2004
- Mark Slutz
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

William Schmitz

Person

Patents Grantslast 30 patents

Systems and methods for assessing timing of PCI signals

Systems and methods for analyzing data of a SAS/SATA device

Parallel bus debugging tool

Methodology to accurately test clock to signal valid and slew rates...

Method and apparatus for generating CRC/parity error in network env...

Systems and methods for analyzing data of an SPI data bus

Method for determining deskew margins in parallel interface receivers

Testing implementation for signal characterization

PCI bus system testing and verification apparatus and method

Patents Applicationslast 30 patents

COMPENSATING FOR JITTER DURING DDR3 MEMORY DELAY LINE TRAINING

Systems and methods for analyzing data of a SAS/SATA device

Parallel bus debugging tool

Systems and methods for assessing timing of PCI signals

Systems and methods for analyzing data of a SAS/SATA device

Systems and methods for analyzing data of an SPI data bus

Method and apparatus for generating CRC/parity error in network env...

Methodology to accurately test clock to signal valid and slew rates...

Method for determining deskew margins in parallel interface receivers