William Schwarz

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Event triggered memory mapped access
- Patent number 8,700,878
- Issue date Apr 15, 2014
- FREESCALE SEMICONDUCTOR, INC.
- William D. Schwarz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for performing built-in-self-test routines using...
- Patent number 7,493,541
- Issue date Feb 17, 2009
- LSI Corporation
- Ghasi R. Agrawal
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and system for performing built-in self-test routines using...
- Patent number 7,260,758
- Issue date Aug 21, 2007
- LSI Corporation
- Ghasi R. Agrawal
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for testing semiconductor devices having built-in self repai...
- Patent number 7,076,699
- Issue date Jul 11, 2006
- LSI Logic Corporation
- Mukesh K. Puri
- G11 - INFORMATION STORAGE
Information Patent Grant
Built-in redundancy analysis for memories with row and column repair
- Patent number 6,795,942
- Issue date Sep 21, 2004
- LSI Logic Corporation
- William D. Schwarz
- G11 - INFORMATION STORAGE
Information Patent Grant
Fast built-in self-repair circuit
- Patent number 6,505,308
- Issue date Jan 7, 2003
- LSI Logic Corporation
- William Schwarz
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-condition BISR test mode for memories with redundancy
- Patent number 6,505,313
- Issue date Jan 7, 2003
- LSI Logic Corporation
- Tuan Phan
- G11 - INFORMATION STORAGE
Information Patent Grant
Built-in self repair circuit with pause for data retention coverage
- Patent number 6,496,947
- Issue date Dec 17, 2002
- LSI Logic Corporation
- William D. Schwarz
- G11 - INFORMATION STORAGE
Information Patent Grant
Built-in self-test unit having a reconfigurable data retention test
- Patent number 6,255,836
- Issue date Jul 3, 2001
- LSI Logic Corporation
- William Schwarz
- G01 - MEASURING TESTING
Information Patent Grant
Redundancy analysis for embedded memories with built-in self test a...
- Patent number 6,067,262
- Issue date May 23, 2000
- LSI Logic Corporation
- V. Swamy Irrinki
- G11 - INFORMATION STORAGE
Information Patent Grant
Reconfigurable built-in self test circuit
- Patent number 5,982,681
- Issue date Nov 9, 1999
- LSI Logic Corporation
- William Schwarz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Refresh sampling built-in self test and repair circuit
- Patent number 5,909,404
- Issue date Jun 1, 1999
- LSI Logic Corporation
- William Schwarz
- G11 - INFORMATION STORAGE
Information Patent Grant
Data retention weak write circuit and method of using same
- Patent number 5,835,429
- Issue date Nov 10, 1998
- LSI Logic Corporation
- William Schwarz
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Event Triggered Memory Mapped Access
- Publication number 20100318752
- Publication date Dec 16, 2010
- FREESCALE SEMICONDUCTOR, INC.
- William D. Schwarz
- G06 - COMPUTING CALCULATING COUNTING

William Schwarz

Person

Patents Grantslast 30 patents

Event triggered memory mapped access

Method and system for performing built-in-self-test routines using...

Method and system for performing built-in self-test routines using...

Method for testing semiconductor devices having built-in self repai...

Built-in redundancy analysis for memories with row and column repair

Fast built-in self-repair circuit

Multi-condition BISR test mode for memories with redundancy

Built-in self repair circuit with pause for data retention coverage

Built-in self-test unit having a reconfigurable data retention test

Redundancy analysis for embedded memories with built-in self test a...

Reconfigurable built-in self test circuit

Refresh sampling built-in self test and repair circuit

Data retention weak write circuit and method of using same

Patents Applicationslast 30 patents

Event Triggered Memory Mapped Access