Willy Rachmady

Person

Beaverton, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Forming an oxide volume within a fin
- Patent number 12,224,202
- Issue date Feb 11, 2025
- Intel Corporation
- Cheng-Ying Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Neighboring gate-all-around integrated circuit structures having co...
- Patent number 12,199,142
- Issue date Jan 14, 2025
- Intel Corporation
- Siddharth Chouksey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Thin-film transistors and MIM capacitors in exclusion zones
- Patent number 12,183,668
- Issue date Dec 31, 2024
- Intel Corporation
- Abhishek A. Sharma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Localized spacer for nanowire transistors and methods of fabrication
- Patent number 12,176,408
- Issue date Dec 24, 2024
- Intel Corporation
- Sudipto Naskar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Non-planar gate all-around device and method of fabrication thereof
- Patent number RE50222
- Issue date Nov 26, 2024
- Sony Group Corporation
- Willy Rachmady
Information Patent Grant
Stacked source-drain-gate connection and process for forming such
- Patent number 12,148,806
- Issue date Nov 19, 2024
- Intel Corporation
- Ehren Mannebach
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Silicon and silicon germanium nanowire structures
- Patent number 12,142,634
- Issue date Nov 12, 2024
- Sony Group Corporation
- Kelin J. Kuhn
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Interconnect techniques for electrically connecting source/drain re...
- Patent number 12,107,085
- Issue date Oct 1, 2024
- Intel Corporation
- Aaron D. Lilak
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked-substrate FPGA semiconductor devices
- Patent number 12,087,750
- Issue date Sep 10, 2024
- Intel Corporation
- Abhishek A. Sharma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Backside contacts for semiconductor devices
- Patent number 12,080,605
- Issue date Sep 3, 2024
- Intel Corporation
- Aaron D. Lilak
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High performance semiconductor oxide material channel regions for NMOS
- Patent number 12,068,319
- Issue date Aug 20, 2024
- Intel Corporation
- Gilbert Dewey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
PN-body-tied field effect transistors
- Patent number 12,051,723
- Issue date Jul 30, 2024
- Intel Corporation
- Aaron D. Lilak
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Nanowire transistor fabrication with hardmask layers
- Patent number 12,046,637
- Issue date Jul 23, 2024
- Sony Group Corporation
- Seung Hoon Sung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Isolation wall stressor structures to improve channel stress and th...
- Patent number 12,033,896
- Issue date Jul 9, 2024
- Intel Corporation
- Aaron D. Lilak
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Epitaxial layer with substantially parallel sides
- Patent number 12,020,929
- Issue date Jun 25, 2024
- Intel Corporation
- Cheng-Ying Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Leave-behind protective layer having secondary purpose
- Patent number 11,996,408
- Issue date May 28, 2024
- Intel Corporation
- Aaron D. Lilak
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Field effect transistors with gate electrode self-aligned to semico...
- Patent number 11,996,447
- Issue date May 28, 2024
- Intel Corporation
- Sean T. Ma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked forksheet transistors
- Patent number 11,996,411
- Issue date May 28, 2024
- Intel Corporation
- Cheng-Ying Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Three-dimensional integrated circuits (3DICs) including bottom gate...
- Patent number 11,996,404
- Issue date May 28, 2024
- Intel Corporation
- Cheng-Ying Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor nanowire device having (111)-plane channel sidewalls
- Patent number 11,990,476
- Issue date May 21, 2024
- Intel Corporation
- Cory E. Weber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Sideways vias in isolation areas to contact interior layers in stac...
- Patent number 11,942,416
- Issue date Mar 26, 2024
- Intel Corporation
- Ehren Mannebach
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Non-silicon N-type and P-type stacked transistors for integrated ci...
- Patent number 11,935,891
- Issue date Mar 19, 2024
- Intel Corporation
- Gilbert Dewey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Ferroelectric gate stack for band-to-band tunneling reduction
- Patent number 11,929,435
- Issue date Mar 12, 2024
- Intel Corporation
- Gilbert Dewey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Top gate recessed channel CMOS thin film transistor in the back end...
- Patent number 11,929,320
- Issue date Mar 12, 2024
- Intel Corporation
- Gilbert Dewey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Transistor with isolation below source and drain
- Patent number 11,923,410
- Issue date Mar 5, 2024
- Intel Corporation
- Willy Rachmady
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Sub-fin leakage reduction for template strained materials
- Patent number 11,923,412
- Issue date Mar 5, 2024
- Intel Corporation
- Rishabh Mehandru
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked source-drain-gate connection and process for forming such
- Patent number 11,916,118
- Issue date Feb 27, 2024
- Intel Corporation
- Ehren Mannebach
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked trigate transistors with dielectric isolation and process f...
- Patent number 11,894,372
- Issue date Feb 6, 2024
- Intel Corporation
- Willy Rachmady
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Deep gate-all-around semiconductor device having germanium or group...
- Patent number 11,894,465
- Issue date Feb 6, 2024
- Google LLC
- Ravi Pillarisetty
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Thin film transistor structures with regrown source and drain
- Patent number 11,887,988
- Issue date Jan 30, 2024
- Intel Corporation
- Ashish Agrawal
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
NANOWIRE TRANSISTOR FABRICATION WITH HARDMASK LAYERS
- Publication number 20240387634
- Publication date Nov 21, 2024
- SONY GROUP CORPORATION
- Seung Hoon Sung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BACKSIDE CONTACTS FOR SEMICONDUCTOR DEVICES
- Publication number 20240371700
- Publication date Nov 7, 2024
- Intel Corporation
- Aaron D. LILAK
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT STRUCTURES WITH SUB-FIN ISOLATION
- Publication number 20240332301
- Publication date Oct 3, 2024
- Intel Corporation
- Willy RACHMADY
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED FORKSHEET TRANSISTORS
- Publication number 20240234422
- Publication date Jul 11, 2024
- Intel Corporation
- Cheng-Ying HUANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SIDEWAYS VIAS IN ISOLATION AREAS TO CONTACT INTERIOR LAYERS IN STAC...
- Publication number 20240162141
- Publication date May 16, 2024
- Intel Corporation
- Ehren MANNEBACH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATION METHODS TO FABRICATE INTERNAL SPACERS FOR NANOWIRE DEVICES
- Publication number 20240153995
- Publication date May 9, 2024
- SONY GROUP CORPORATION
- Seiyon KIM
- B82 - NANO-TECHNOLOGY
Information Patent Application
STACKED SOURCE-DRAIN-GATE CONNECTION AND PROCESS FOR FORMING SUCH
- Publication number 20240145557
- Publication date May 2, 2024
- Intel Corporation
- Ehren MANNEBACH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TOP GATE RECESSED CHANNEL CMOS THIN FILM TRANSISTOR AND METHODS OF...
- Publication number 20240136277
- Publication date Apr 25, 2024
- Intel Corporation
- Gilbert Dewey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TRANSISTOR WITH ISOLATION BELOW SOURCE AND DRAIN
- Publication number 20240113161
- Publication date Apr 4, 2024
- Intel Corporation
- Willy Rachmady
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING INSULATOR FIN...
- Publication number 20240088254
- Publication date Mar 14, 2024
- Intel Corporation
- Aaron D. LILAK
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING DEPOPULATED CH...
- Publication number 20240047559
- Publication date Feb 8, 2024
- Intel Corporation
- Willy RACHMADY
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
AMORPHIZATION AND REGROWTH OF SOURCE-DRAIN REGIONS FROM THE BOTTOM-...
- Publication number 20240006489
- Publication date Jan 4, 2024
- Intel Corporation
- Aaron LILAK
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED EMBEDDED SOURCE AND DRAIN CONTACTS
- Publication number 20230420528
- Publication date Dec 28, 2023
- Intel Corporation
- Nitesh Kumar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DUAL METAL SILICIDE FOR STACKED TRANSISTOR DEVICES
- Publication number 20230402507
- Publication date Dec 14, 2023
- Intel Corporation
- Rohit Galatage
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SOURCE AND DRAIN CONTACTS FORMED USING SACRIFICIAL REGIONS OF SOURC...
- Publication number 20230402513
- Publication date Dec 14, 2023
- Intel Corporation
- Rohit Galatage
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELECTIVE REMOVAL OF CHANNEL BODIES IN STACKED GATE-ALL-AROUND (GAA...
- Publication number 20230395678
- Publication date Dec 7, 2023
- Intel Corporation
- Munzarin F. Qayyum
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
REMOVAL OF UPPER CHANNEL BODIES IN STACKED GATE-ALL-AROUND (GAA) DE...
- Publication number 20230395697
- Publication date Dec 7, 2023
- Intel Corporation
- Nicole K. Thomas
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D SOURCE AND DRAIN CONTACTS TUNED FOR VERTICALLY STACKED PMOS AND...
- Publication number 20230395718
- Publication date Dec 7, 2023
- Intel Corporation
- Willy Rachmady
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D SOURCE AND DRAIN CONTACTS TUNED FOR PMOS AND NMOS
- Publication number 20230395717
- Publication date Dec 7, 2023
- Intel Corporation
- Willy Rachmady
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FORMING AN OXIDE VOLUME WITHIN A FIN
- Publication number 20230377947
- Publication date Nov 23, 2023
- Intel Corporation
- Cheng-Ying HUANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING DEPOPULATED CH...
- Publication number 20230369399
- Publication date Nov 16, 2023
- Intel Corporation
- Ehren Mannebach
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTERCONNECT TECHNIQUES FOR ELECTRICALLY CONNECTING SOURCE/DRAIN RE...
- Publication number 20230352481
- Publication date Nov 2, 2023
- Intel Corporation
- AARON D. LILAK
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NANOWIRE TRANSISTOR FABRICATION WITH HARDMASK LAYERS
- Publication number 20230335594
- Publication date Oct 19, 2023
- SONY CORPORATION
- Seung Hoon Sung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TRANSISTOR BODY-INDUCED BODY LEAKAGE MITIGATION AT LOW TEMPERATURE
- Publication number 20230317851
- Publication date Oct 5, 2023
- Intel Corporation
- Abhishek Anil Sharma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TRANSISTOR ARRANGEMENTS WITH REDUCED DIMENSIONS AT THE GATE
- Publication number 20230290831
- Publication date Sep 14, 2023
- Intel Corporation
- Abhishek A. Sharma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TRANSISTOR GATE STACKS WITH DIPOLE LAYERS
- Publication number 20230261107
- Publication date Aug 17, 2023
- Intel Corporation
- Abhishek A. Sharma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED SOURCE-DRAIN-GATE CONNECTION AND PROCESS FOR FORMING SUCH
- Publication number 20230238436
- Publication date Jul 27, 2023
- Intel Corporation
- Ehren MANNEBACH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SOURCE OR DRAIN METALLIZATION PRIOR TO CONTACT FORMATION IN STACKED...
- Publication number 20230197777
- Publication date Jun 22, 2023
- Intel Corporation
- Gilbert Dewey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WRAP-AROUND CONTACTS FOR STACKED TRANSISTORS
- Publication number 20230197815
- Publication date Jun 22, 2023
- Intel Corporation
- Cheng-Ying Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FRONTSIDE AND BACKSIDE EPI CONTACT
- Publication number 20230197569
- Publication date Jun 22, 2023
- Intel Corporation
- Gilbert Dewey
- H01 - BASIC ELECTRIC ELEMENTS

Willy Rachmady

Person

Patents Grantslast 30 patents

Forming an oxide volume within a fin

Neighboring gate-all-around integrated circuit structures having co...

Thin-film transistors and MIM capacitors in exclusion zones

Localized spacer for nanowire transistors and methods of fabrication

Non-planar gate all-around device and method of fabrication thereof

Stacked source-drain-gate connection and process for forming such

Silicon and silicon germanium nanowire structures

Interconnect techniques for electrically connecting source/drain re...

Stacked-substrate FPGA semiconductor devices

Backside contacts for semiconductor devices

High performance semiconductor oxide material channel regions for NMOS

PN-body-tied field effect transistors

Nanowire transistor fabrication with hardmask layers

Isolation wall stressor structures to improve channel stress and th...

Epitaxial layer with substantially parallel sides

Leave-behind protective layer having secondary purpose

Field effect transistors with gate electrode self-aligned to semico...

Stacked forksheet transistors

Three-dimensional integrated circuits (3DICs) including bottom gate...

Semiconductor nanowire device having (111)-plane channel sidewalls

Sideways vias in isolation areas to contact interior layers in stac...

Non-silicon N-type and P-type stacked transistors for integrated ci...

Ferroelectric gate stack for band-to-band tunneling reduction

Top gate recessed channel CMOS thin film transistor in the back end...

Transistor with isolation below source and drain

Sub-fin leakage reduction for template strained materials

Stacked source-drain-gate connection and process for forming such

Stacked trigate transistors with dielectric isolation and process f...

Deep gate-all-around semiconductor device having germanium or group...

Thin film transistor structures with regrown source and drain

Patents Applicationslast 30 patents

NANOWIRE TRANSISTOR FABRICATION WITH HARDMASK LAYERS

BACKSIDE CONTACTS FOR SEMICONDUCTOR DEVICES

INTEGRATED CIRCUIT STRUCTURES WITH SUB-FIN ISOLATION

STACKED FORKSHEET TRANSISTORS

SIDEWAYS VIAS IN ISOLATION AREAS TO CONTACT INTERIOR LAYERS IN STAC...

INTEGRATION METHODS TO FABRICATE INTERNAL SPACERS FOR NANOWIRE DEVICES

STACKED SOURCE-DRAIN-GATE CONNECTION AND PROCESS FOR FORMING SUCH

TOP GATE RECESSED CHANNEL CMOS THIN FILM TRANSISTOR AND METHODS OF...

TRANSISTOR WITH ISOLATION BELOW SOURCE AND DRAIN

GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING INSULATOR FIN...

GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING DEPOPULATED CH...

AMORPHIZATION AND REGROWTH OF SOURCE-DRAIN REGIONS FROM THE BOTTOM-...

SELF-ALIGNED EMBEDDED SOURCE AND DRAIN CONTACTS

DUAL METAL SILICIDE FOR STACKED TRANSISTOR DEVICES

SOURCE AND DRAIN CONTACTS FORMED USING SACRIFICIAL REGIONS OF SOURC...

SELECTIVE REMOVAL OF CHANNEL BODIES IN STACKED GATE-ALL-AROUND (GAA...

REMOVAL OF UPPER CHANNEL BODIES IN STACKED GATE-ALL-AROUND (GAA) DE...

3D SOURCE AND DRAIN CONTACTS TUNED FOR VERTICALLY STACKED PMOS AND...

3D SOURCE AND DRAIN CONTACTS TUNED FOR PMOS AND NMOS

FORMING AN OXIDE VOLUME WITHIN A FIN

GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING DEPOPULATED CH...

INTERCONNECT TECHNIQUES FOR ELECTRICALLY CONNECTING SOURCE/DRAIN RE...

NANOWIRE TRANSISTOR FABRICATION WITH HARDMASK LAYERS

TRANSISTOR BODY-INDUCED BODY LEAKAGE MITIGATION AT LOW TEMPERATURE

TRANSISTOR ARRANGEMENTS WITH REDUCED DIMENSIONS AT THE GATE

TRANSISTOR GATE STACKS WITH DIPOLE LAYERS

STACKED SOURCE-DRAIN-GATE CONNECTION AND PROCESS FOR FORMING SUCH

SOURCE OR DRAIN METALLIZATION PRIOR TO CONTACT FORMATION IN STACKED...

WRAP-AROUND CONTACTS FOR STACKED TRANSISTORS

FRONTSIDE AND BACKSIDE EPI CONTACT