Wilson K. Yee

Person

Tracy, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Programmable integrated circuit having built in test circuit
- Patent number 7,786,749
- Issue date Aug 31, 2010
- Sillcon Storage Technology, Inc.
- Tsung-Lu Syu
- G01 - MEASURING TESTING
Information Patent Grant
Processing data packets at a storage service module of a switch
- Patent number 7,460,528
- Issue date Dec 2, 2008
- Brocade Communications Systems, Inc.
- Joseph I. Chamdani
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Programmable interface for a configurable system bus
- Patent number 6,754,760
- Issue date Jun 22, 2004
- Xilinx, Inc.
- Wilson Yee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for PLD swapping
- Patent number 6,526,466
- Issue date Feb 25, 2003
- Xilinx, Inc.
- Scott O. Frake
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bank-based configuration and reconfiguration for programmable logic...
- Patent number 6,459,646
- Issue date Oct 1, 2002
- Triscend Corporation
- Wilson Yee
- G11 - INFORMATION STORAGE
Information Patent Grant
Structure and method for generating a clock enable signal in a PLD
- Patent number 6,218,864
- Issue date Apr 17, 2001
- Xilinx, Inc.
- Steven P. Young
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integrated circuit with field programmable and application specific...
- Patent number 6,094,065
- Issue date Jul 25, 2000
- Xilinx, Inc.
- Danesh Tavana
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
FPGA architecture with repeatable titles including routing matrices...
- Patent number 5,883,525
- Issue date Mar 16, 1999
- Xilinx, Inc.
- Danesh Tavana
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integrated circuit with field programmable and application specific...
- Patent number 5,825,202
- Issue date Oct 20, 1998
- Xilinx, Inc.
- Danesh Tavana
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
FPGA architecture with repeatable tiles including routing matrices...
- Patent number 5,682,107
- Issue date Oct 28, 1997
- Xilinx, Inc.
- Danesh Tavana
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable scan chain testing structure and method
- Patent number 5,675,589
- Issue date Oct 7, 1997
- Xilinx, Inc.
- Wilson K. Yee
- G01 - MEASURING TESTING
Information Patent Grant
Programmable scan chain testing structure and method
- Patent number 5,550,843
- Issue date Aug 27, 1996
- Xilinx, Inc.
- Wilson K. Yee
- G01 - MEASURING TESTING
Information Patent Grant
Field programmable gate array providing contention free configurati...
- Patent number 5,453,706
- Issue date Sep 26, 1995
- Xilinx, Inc.
- Wilson K. Yee
- H03 - BASIC ELECTRONIC CIRCUITRY

Wilson K. Yee

Person

Patents Grantslast 30 patents

Programmable integrated circuit having built in test circuit

Processing data packets at a storage service module of a switch

Programmable interface for a configurable system bus

Method and system for PLD swapping

Bank-based configuration and reconfiguration for programmable logic...

Structure and method for generating a clock enable signal in a PLD

Integrated circuit with field programmable and application specific...

FPGA architecture with repeatable titles including routing matrices...

Integrated circuit with field programmable and application specific...

FPGA architecture with repeatable tiles including routing matrices...

Programmable scan chain testing structure and method

Programmable scan chain testing structure and method

Field programmable gate array providing contention free configurati...