Wilson Pradeep

Person

Bangalore, IN

People

Patents Grantslast 30 patents

Information Patent Grant
Clock shaper circuit for transition fault testing
- Patent number 12,216,160
- Issue date Feb 4, 2025
- Texas Instruments Incorporated
- Wilson Pradeep
- G11 - INFORMATION STORAGE
Information Patent Grant
Path based controls for ATE mode testing of multicell memory circuit
- Patent number 11,933,844
- Issue date Mar 19, 2024
- Texas Instruments Incorporated
- Wilson Pradeep
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic generation of ATPG mode signals for testing multipath memor...
- Patent number 11,879,940
- Issue date Jan 23, 2024
- Texas Instruments Incorporated
- Wilson Pradeep
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Delay fault testing of pseudo static controls
- Patent number 11,768,726
- Issue date Sep 26, 2023
- Texas Instruments Incorporated
- Aravinda Acharya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Control data registers for scan testing
- Patent number 11,680,984
- Issue date Jun 20, 2023
- Texas Instruments Incorporated
- Wilson Pradeep
- G01 - MEASURING TESTING
Information Patent Grant
Clock shaper circuit for transition fault testing
- Patent number 11,604,221
- Issue date Mar 14, 2023
- Texas Instruments Incorporated
- Wilson Pradeep
- G11 - INFORMATION STORAGE
Information Patent Grant
Phase controlled codec block scan of a partitioned circuit device
- Patent number 11,519,964
- Issue date Dec 6, 2022
- Texas Instruments Incorporated
- Prakash Narayanan
- G01 - MEASURING TESTING
Information Patent Grant
Testing of integrated circuits during at-speed mode of operation
- Patent number 11,333,707
- Issue date May 17, 2022
- Texas Instruments Incorporated
- Khushboo Agarwal
- G01 - MEASURING TESTING
Information Patent Grant
Multiple input signature register analysis for digital circuitry
- Patent number 11,209,481
- Issue date Dec 28, 2021
- Texas Instruments Incorporated
- Naman Maheshwari
- G01 - MEASURING TESTING
Information Patent Grant
False path timing exception handler circuit
- Patent number 11,194,944
- Issue date Dec 7, 2021
- Texas Instruments Incorporated
- Wilson Pradeep
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Delay fault testing of pseudo static controls
- Patent number 11,194,645
- Issue date Dec 7, 2021
- Texas Instruments Incorporated
- Aravinda Acharya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Phase controlled codec block scan of a partitioned circuit device
- Patent number 11,073,557
- Issue date Jul 27, 2021
- Texas Instruments Incorporated
- Prakash Narayanan
- G01 - MEASURING TESTING
Information Patent Grant
Dynamic generation of ATPG mode signals for testing multipath memor...
- Patent number 11,073,553
- Issue date Jul 27, 2021
- Texas Instruments Incorporated
- Wilson Pradeep
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Path based controls for ATE mode testing of multicell memory circuit
- Patent number 11,047,910
- Issue date Jun 29, 2021
- Texas Instruments Incorporated
- Wilson Pradeep
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
False path timing exception handler circuit
- Patent number 10,776,546
- Issue date Sep 15, 2020
- Texas Instruments Incorporated
- Wilson Pradeep
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Delay fault testing of pseudo static controls
- Patent number 10,579,454
- Issue date Mar 3, 2020
- Texas Instruments Incorporated
- Aravinda Acharya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for test insertion points
- Patent number 10,473,717
- Issue date Nov 12, 2019
- Texas Instruments Incorporated
- Wilson Pradeep
- G01 - MEASURING TESTING
Information Patent Grant
False path timing exception handler circuit
- Patent number 10,331,826
- Issue date Jun 25, 2019
- Texas Instruments Incorporated
- Wilson Pradeep
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple input signature register analysis for digital circuitry
- Patent number 10,184,980
- Issue date Jan 22, 2019
- Texas Instruments Incorporated
- Naman Maheshwari
- G01 - MEASURING TESTING
Information Patent Grant
Frequency scaled segmented scan chain for integrated circuits
- Patent number 9,535,123
- Issue date Jan 3, 2017
- Texas Instruments Incorporated
- Rajesh Kumar Mittal
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
Logical Memory Repair with a Shared Physical Memory
- Publication number 20240203517
- Publication date Jun 20, 2024
- Google LLC
- Wilson Pradeep
- G11 - INFORMATION STORAGE
Information Patent Application
CLOCK SHAPER CIRCUIT FOR TRANSITION FAULT TESTING
- Publication number 20230243887
- Publication date Aug 3, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Wilson Pradeep
- G11 - INFORMATION STORAGE
Information Patent Application
DELAY FAULT TESTING OF PSEUDO STATIC CONTROLS
- Publication number 20220091919
- Publication date Mar 24, 2022
- TEXAS INSTRUMENTS INCORPORATED
- ARAVINDA ACHARYA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC GENERATION OF ATPG MODE SIGNALS FOR TESTING MULTIPATH MEMOR...
- Publication number 20210318378
- Publication date Oct 14, 2021
- TEXAS INSTRUMENTS INCORPORATED
- WILSON PRADEEP
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PHASE CONTROLLED CODEC BLOCK SCAN OF A PARTITIONED CIRCUIT DEVICE
- Publication number 20210311121
- Publication date Oct 7, 2021
- TEXAS INSTRUMENTS INCORPORATED
- PRAKASH NARAYANAN
- G01 - MEASURING TESTING
Information Patent Application
PATH BASED CONTROLS FOR ATE MODE TESTING OF MULTICELL MEMORY CIRCUIT
- Publication number 20210278459
- Publication date Sep 9, 2021
- TEXAS INSTRUMENTS INCORPORATED
- WILSON PRADEEP
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FALSE PATH TIMING EXCEPTION HANDLER CIRCUIT
- Publication number 20200372197
- Publication date Nov 26, 2020
- TEXAS INSTRUMENTS INCORPORATED
- WILSON PRADEEP
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PHASE CONTROLLED CODEC BLOCK SCAN OF A PARTITIONED CIRCUIT DEVICE
- Publication number 20200355744
- Publication date Nov 12, 2020
- TEXAS INSTRUMENTS INCORPORATED
- PRAKASH NARAYANAN
- G01 - MEASURING TESTING
Information Patent Application
DELAY FAULT TESTING OF PSEUDO STATIC CONTROLS
- Publication number 20200142768
- Publication date May 7, 2020
- TEXAS INSTRUMENTS INCORPORATED
- ARAVINDA ACHARYA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TESTING OF INTEGRATED CIRCUITS DURING AT-SPEED MODE OF OPERATION
- Publication number 20200132763
- Publication date Apr 30, 2020
- TEXAS INSTRUMENTS INCORPORATED
- Khushboo Agarwal
- G01 - MEASURING TESTING
Information Patent Application
FALSE PATH TIMING EXCEPTION HANDLER CIRCUIT
- Publication number 20190266303
- Publication date Aug 29, 2019
- TEXAS INSTRUMENTS INCORPORATED
- WILSON PRADEEP
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PATH BASED CONTROLS FOR ATE MODE TESTING OF MULTICELL MEMORY CIRCUIT
- Publication number 20190204382
- Publication date Jul 4, 2019
- TEXAS INSTRUMENTS INCORPORATED
- WILSON PRADEEP
- G01 - MEASURING TESTING
Information Patent Application
DYNAMIC GENERATION OF ATPG MODE SIGNALS FOR TESTING MULTIPATH MEMOR...
- Publication number 20190206507
- Publication date Jul 4, 2019
- TEXAS INSTRUMENTS INCORPORATED
- WILSON PRADEEP
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLE INPUT SIGNATURE REGISTER ANALYSIS FOR DIGITAL CIRCUITRY
- Publication number 20190113566
- Publication date Apr 18, 2019
- TEXAS INSTRUMENTS INCORPORATED
- NAMAN MAHESHWARI
- G01 - MEASURING TESTING
Information Patent Application
DELAY FAULT TESTING OF PSEUDO STATIC CONTROLS
- Publication number 20180307553
- Publication date Oct 25, 2018
- TEXAS INSTRUMENTS INCORPORATED
- ARAVINDA ACHARYA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FALSE PATH TIMING EXCEPTION HANDLER CIRCUIT
- Publication number 20180307788
- Publication date Oct 25, 2018
- TEXAS INSTRUMENTS INCORPORATED
- WILSON PRADEEP
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and Apparatus for Test Insertion Points
- Publication number 20180128877
- Publication date May 10, 2018
- TEXAS INSTRUMENTS INCORPORATED
- Wilson Pradeep
- G01 - MEASURING TESTING
Information Patent Application
MULTIPLE INPUT SIGNATURE REGISTER ANALYSIS FOR DIGITAL CIRCUITRY
- Publication number 20180067164
- Publication date Mar 8, 2018
- TEXAS INSTRUMENTS INCORPORATED
- NAMAN MAHESHWARI
- G01 - MEASURING TESTING
Information Patent Application
Frequency Scaled Segmented Scan Chain for Integrated Circuits
- Publication number 20160266202
- Publication date Sep 15, 2016
- TEXAS INSTRUMENTS INCORPORATED
- Rajesh Kumar Mittal
- G01 - MEASURING TESTING
Information Patent Application
TESTING OF INTEGRATED CIRCUITS DURING AT-SPEED MODE OF OPERATION
- Publication number 20150212152
- Publication date Jul 30, 2015
- TEXAS INSTRUMENTS INCORPORATED
- Khushboo Agarwal
- G01 - MEASURING TESTING

Wilson Pradeep

Person

Patents Grantslast 30 patents

Clock shaper circuit for transition fault testing

Path based controls for ATE mode testing of multicell memory circuit

Dynamic generation of ATPG mode signals for testing multipath memor...

Delay fault testing of pseudo static controls

Control data registers for scan testing

Clock shaper circuit for transition fault testing

Phase controlled codec block scan of a partitioned circuit device

Testing of integrated circuits during at-speed mode of operation

Multiple input signature register analysis for digital circuitry

False path timing exception handler circuit

Delay fault testing of pseudo static controls

Phase controlled codec block scan of a partitioned circuit device

Dynamic generation of ATPG mode signals for testing multipath memor...

Path based controls for ATE mode testing of multicell memory circuit

False path timing exception handler circuit

Delay fault testing of pseudo static controls

Methods and apparatus for test insertion points

False path timing exception handler circuit

Multiple input signature register analysis for digital circuitry

Frequency scaled segmented scan chain for integrated circuits

Patents Applicationslast 30 patents

Logical Memory Repair with a Shared Physical Memory

CLOCK SHAPER CIRCUIT FOR TRANSITION FAULT TESTING

DELAY FAULT TESTING OF PSEUDO STATIC CONTROLS

DYNAMIC GENERATION OF ATPG MODE SIGNALS FOR TESTING MULTIPATH MEMOR...

PHASE CONTROLLED CODEC BLOCK SCAN OF A PARTITIONED CIRCUIT DEVICE

PATH BASED CONTROLS FOR ATE MODE TESTING OF MULTICELL MEMORY CIRCUIT

FALSE PATH TIMING EXCEPTION HANDLER CIRCUIT

PHASE CONTROLLED CODEC BLOCK SCAN OF A PARTITIONED CIRCUIT DEVICE

DELAY FAULT TESTING OF PSEUDO STATIC CONTROLS

TESTING OF INTEGRATED CIRCUITS DURING AT-SPEED MODE OF OPERATION

FALSE PATH TIMING EXCEPTION HANDLER CIRCUIT

PATH BASED CONTROLS FOR ATE MODE TESTING OF MULTICELL MEMORY CIRCUIT

DYNAMIC GENERATION OF ATPG MODE SIGNALS FOR TESTING MULTIPATH MEMOR...

MULTIPLE INPUT SIGNATURE REGISTER ANALYSIS FOR DIGITAL CIRCUITRY

DELAY FAULT TESTING OF PSEUDO STATIC CONTROLS

FALSE PATH TIMING EXCEPTION HANDLER CIRCUIT

Methods and Apparatus for Test Insertion Points

MULTIPLE INPUT SIGNATURE REGISTER ANALYSIS FOR DIGITAL CIRCUITRY

Frequency Scaled Segmented Scan Chain for Integrated Circuits

TESTING OF INTEGRATED CIRCUITS DURING AT-SPEED MODE OF OPERATION