Wing-Kai Chow

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Multi-threaded network routing based on partitioning
- Patent number 11,928,500
- Issue date Mar 12, 2024
- Cadence Design Systems, Inc.
- Wing-Kai Chow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit design routing based on routing demand adjustment
- Patent number 11,461,530
- Issue date Oct 4, 2022
- Cadence Design Systems, Inc.
- Mateus Paiva Fogaça
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Routing based on pin placement within routing blockage
- Patent number 11,030,377
- Issue date Jun 8, 2021
- Cadence Design Systems, Inc.
- Wing-Kai Chow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Routing congestion based on layer-assigned net and placement blockage
- Patent number 10,997,352
- Issue date May 4, 2021
- Cadence Design Systems, Inc.
- Gracieli Posser
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Routing congestion based on via spacing and pin density
- Patent number 10,885,257
- Issue date Jan 5, 2021
- Cadence Design Systems, Inc.
- Gracieli Posser
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock pin to clock tap assignment based on circuit device connectivity
- Patent number 10,860,775
- Issue date Dec 8, 2020
- Cadence Design Systems, Inc.
- Wing-Kai Chow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for routing in an integrated circuit design
- Patent number 10,755,024
- Issue date Aug 25, 2020
- Cadence Design Systems, Inc.
- Wing Kai Chow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit design routing based on parallel run length rules
- Patent number 10,685,164
- Issue date Jun 16, 2020
- Cadence Design Systems, Inc.
- Yi-Xiao Ding
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit routing based on enhanced topology
- Patent number 10,460,063
- Issue date Oct 29, 2019
- Cadence Design Systems, Inc.
- Wen-Hao Liu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Routing framework to resolve single-entry constraint violations for...
- Patent number 10,460,066
- Issue date Oct 29, 2019
- Cadence Design Systems, Inc.
- Gracieli Posser
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Routing topology generation using spine-like tree structure
- Patent number 10,460,065
- Issue date Oct 29, 2019
- Cadence Design Systems, Inc.
- Wen-Hao Liu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for clustering pins for power
- Patent number 10,289,792
- Issue date May 14, 2019
- Cadence Design Systems, Inc.
- Wing-Kai Chow
- G06 - COMPUTING CALCULATING COUNTING

Wing-Kai Chow

Person

Patents Grantslast 30 patents

Multi-threaded network routing based on partitioning

Circuit design routing based on routing demand adjustment

Routing based on pin placement within routing blockage

Routing congestion based on layer-assigned net and placement blockage

Routing congestion based on via spacing and pin density

Clock pin to clock tap assignment based on circuit device connectivity

System and method for routing in an integrated circuit design

Circuit design routing based on parallel run length rules

Integrated circuit routing based on enhanced topology

Routing framework to resolve single-entry constraint violations for...

Routing topology generation using spine-like tree structure

Systems and methods for clustering pins for power