Witawat Wijaranakula

Person

Vancouver, WA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Silicon and oxygen ion co-implanation for metallic gettering in epi...
- Patent number 6,569,749
- Issue date May 27, 2003
- SEH America, Inc.
- Witawat Wijaranakula
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Silicon and oxygen ion co-implantation for metallic gettering in ep...
- Patent number 6,022,793
- Issue date Feb 8, 2000
- SEH America, Inc.
- Witawat Wijaranakula
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for manufacturing a wafer having a microdefect-free layer of...
- Patent number 5,961,713
- Issue date Oct 5, 1999
- SEH America, Inc.
- Witawat Wijaranakula
- C30 - CRYSTAL GROWTH
Information Patent Grant
Method for improving mechanical strength of the neck section of czo...
- Patent number 5,865,887
- Issue date Feb 2, 1999
- SEH America, Inc.
- Witawat Wijaranakula
- C30 - CRYSTAL GROWTH
Information Patent Grant
Apparatus for improving mechanical strength of the neck section of...
- Patent number 5,827,367
- Issue date Oct 27, 1998
- SEH America
- Witawat Wijaranakula
- C30 - CRYSTAL GROWTH
Information Patent Grant
Method for producing semiconductor wafers with low light scattering...
- Patent number 5,629,216
- Issue date May 13, 1997
- SEH America, Inc.
- Witawat Wijaranakula
- C30 - CRYSTAL GROWTH
Information Patent Grant
Method for manufacturing a calibration wafer having a microdefect-f...
- Patent number 5,611,855
- Issue date Mar 18, 1997
- SEH America, Inc.
- Witawat Wijaranakula
- C30 - CRYSTAL GROWTH
Information Patent Grant
Epitaxial silicon wafers for CMOS integrated circuits
- Patent number 5,306,939
- Issue date Apr 26, 1994
- SEH America
- Kiyoshi Mitani
- H01 - BASIC ELECTRIC ELEMENTS

Witawat Wijaranakula

Person

Patents Grantslast 30 patents

Silicon and oxygen ion co-implanation for metallic gettering in epi...

Silicon and oxygen ion co-implantation for metallic gettering in ep...

Method for manufacturing a wafer having a microdefect-free layer of...

Method for improving mechanical strength of the neck section of czo...

Apparatus for improving mechanical strength of the neck section of...

Method for producing semiconductor wafers with low light scattering...

Method for manufacturing a calibration wafer having a microdefect-f...

Epitaxial silicon wafers for CMOS integrated circuits