Wolfgang Penth

Person

Herrenberg, DE

People

Patents Grantslast 30 patents

Information Patent Grant
Digital logic circuit for deterring race violations at an array tes...
- Patent number 11,043,938
- Issue date Jun 22, 2021
- International Business Machines Corporation
- Harry Barowski
- G01 - MEASURING TESTING
Information Patent Grant
RAM memory with pre-charging circuitry coupled to global bit-lines...
- Patent number 10,984,843
- Issue date Apr 20, 2021
- International Business Machines Corporation
- Martin Bernhard Schmidt
- G11 - INFORMATION STORAGE
Information Patent Grant
Digital logic circuit for deterring race violations at an array tes...
- Patent number 10,587,248
- Issue date Mar 10, 2020
- International Business Machines Corporation
- Harry Barowski
- G11 - INFORMATION STORAGE
Information Patent Grant
Digital logic circuit for deterring race violations at an array tes...
- Patent number 10,367,481
- Issue date Jul 30, 2019
- International Business Machines Corporation
- Harry Barowski
- G01 - MEASURING TESTING
Information Patent Grant
Automated stressing and testing of semiconductor memory cells
- Patent number 9,837,142
- Issue date Dec 5, 2017
- International Business Machines Corporation
- Yuen H. Chan
- G11 - INFORMATION STORAGE
Information Patent Grant
Automated stressing and testing of semiconductor memory cells
- Patent number 9,805,823
- Issue date Oct 31, 2017
- International Business Machines Corporation
- Yuen H. Chan
- G11 - INFORMATION STORAGE
Information Patent Grant
Automatic built-in self test for memory arrays
- Patent number 9,715,944
- Issue date Jul 25, 2017
- International Business Machines Corporation
- Lior Binyamini
- G11 - INFORMATION STORAGE
Information Patent Grant
Stressing and testing semiconductor memory cells
- Patent number 9,704,567
- Issue date Jul 11, 2017
- International Business Machines Corporation
- Michael B. Kugel
- G11 - INFORMATION STORAGE
Information Patent Grant
Write address synchronization in 2 read/1write SRAM arrays
- Patent number 9,437,285
- Issue date Sep 6, 2016
- International Business Machines Corporation
- Harry Barowski
- G11 - INFORMATION STORAGE
Information Patent Grant
Write address synchronization in 2 read/1write SRAM arrays
- Patent number 9,406,375
- Issue date Aug 2, 2016
- International Business Machines Corporation
- Harry Barowski
- G11 - INFORMATION STORAGE
Information Patent Grant
Boost circuit for generating an adjustable boost voltage
- Patent number 8,493,812
- Issue date Jul 23, 2013
- International Business Machines Corporation
- Osama Dengler
- G11 - INFORMATION STORAGE
Information Patent Grant
Reduced power consumption memory circuitry
- Patent number 8,422,313
- Issue date Apr 16, 2013
- International Business Machines Corporation
- Stefan Buettner
- G11 - INFORMATION STORAGE
Information Patent Grant
Asymmetrical random access memory cell, memory comprising asymmetri...
- Patent number 7,495,949
- Issue date Feb 24, 2009
- International Business Machines Corporation
- Stefan Buettner
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
REDUCING MEMORY POWER CONSUMPTION
- Publication number 20200279593
- Publication date Sep 3, 2020
- International Business Machines Corporation
- Martin Bernhard Schmidt
- G11 - INFORMATION STORAGE
Information Patent Application
DIGITAL LOGIC CIRCUIT FOR DETERRING RACE VIOLATIONS AT AN ARRAY TES...
- Publication number 20200127649
- Publication date Apr 23, 2020
- International Business Machines Corporation
- Harry Barowski
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DIGITAL LOGIC CIRCUIT
- Publication number 20180212594
- Publication date Jul 26, 2018
- International Business Machines Corporation
- Harry Barowski
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DIGITAL LOGIC CIRCUIT
- Publication number 20180212595
- Publication date Jul 26, 2018
- International Business Machines Corporation
- Harry Barowski
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
REDUCED POWER CONSUMPTION MEMORY CIRCUITRY
- Publication number 20120155188
- Publication date Jun 21, 2012
- International Business Machines Corporation
- Stefan Buettner
- G11 - INFORMATION STORAGE
Information Patent Application
BOOST CIRCUIT FOR GENERATING AN ADJUSTABLE BOOST VOLTAGE
- Publication number 20120106237
- Publication date May 3, 2012
- International Business Machines Corporation
- OSAMA DENGLER
- G11 - INFORMATION STORAGE
Information Patent Application
Asymmetrical Random Access Memory Cell, Memory Comprising Asymmetri...
- Publication number 20070189061
- Publication date Aug 16, 2007
- Stefan Buettner
- G11 - INFORMATION STORAGE

Wolfgang Penth

Person

Patents Grantslast 30 patents

Digital logic circuit for deterring race violations at an array tes...

RAM memory with pre-charging circuitry coupled to global bit-lines...

Digital logic circuit for deterring race violations at an array tes...

Digital logic circuit for deterring race violations at an array tes...

Automated stressing and testing of semiconductor memory cells

Automated stressing and testing of semiconductor memory cells

Automatic built-in self test for memory arrays

Stressing and testing semiconductor memory cells

Write address synchronization in 2 read/1write SRAM arrays

Write address synchronization in 2 read/1write SRAM arrays

Boost circuit for generating an adjustable boost voltage

Reduced power consumption memory circuitry

Asymmetrical random access memory cell, memory comprising asymmetri...

Patents Applicationslast 30 patents

REDUCING MEMORY POWER CONSUMPTION

DIGITAL LOGIC CIRCUIT FOR DETERRING RACE VIOLATIONS AT AN ARRAY TES...

DIGITAL LOGIC CIRCUIT

DIGITAL LOGIC CIRCUIT

REDUCED POWER CONSUMPTION MEMORY CIRCUITRY

BOOST CIRCUIT FOR GENERATING AN ADJUSTABLE BOOST VOLTAGE

Asymmetrical Random Access Memory Cell, Memory Comprising Asymmetri...