Xavier Vera

Person

Barcelona, ES

People

Patents Grantslast 30 patents

Information Patent Grant
Disabling cache portions during low voltage operations
- Patent number 10,528,473
- Issue date Jan 7, 2020
- Intel Corporation
- Christopher Wilkerson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Capacity register file
- Patent number 10,020,037
- Issue date Jul 10, 2018
- Intel Corporation
- Jaume Abella
- G11 - INFORMATION STORAGE
Information Patent Grant
Disabling cache portions during low voltage operations
- Patent number 9,678,878
- Issue date Jun 13, 2017
- Intel Corporation
- Christopher Wilkerson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Enforcing different operational configurations for different tasks...
- Patent number 9,619,309
- Issue date Apr 11, 2017
- Intel Corporation
- Enric H. Abellanas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Traffic control on an on-chip network
- Patent number 9,608,922
- Issue date Mar 28, 2017
- Intel Corporation
- Matteo Monchiero
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Register error protection through binary translation
- Patent number 9,405,647
- Issue date Aug 2, 2016
- Intel Corporation
- Xavier Vera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fault-aware mapping for shared last level cache (LLC)
- Patent number 9,286,172
- Issue date Mar 15, 2016
- Intel Corporation
- Tanausu Ramirez
- G11 - INFORMATION STORAGE
Information Patent Grant
Increased error correction for cache memories through adaptive repl...
- Patent number 9,176,895
- Issue date Nov 3, 2015
- Intel Corporation
- Xavier Vera
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Recovering from data errors using implicit redundancy
- Patent number 9,170,947
- Issue date Oct 27, 2015
- Intel Corporation
- Xavier Vera
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Content-aware caches for reliability
- Patent number 9,112,537
- Issue date Aug 18, 2015
- Intel Corporation
- Tanausu Ramirez
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Vulnerability estimation for cache memory
- Patent number 9,075,904
- Issue date Jul 7, 2015
- Intel Corporation
- Javier Carretero Casado
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Selective provision of error correction for memory
- Patent number 9,071,281
- Issue date Jun 30, 2015
- Intel Corporation
- Javier Carretero Casado
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Banking of reliability metrics
- Patent number 9,043,659
- Issue date May 26, 2015
- Intel Corporation
- Enric Herrero Abellanas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reducing aging effect on registers
- Patent number 8,578,137
- Issue date Nov 5, 2013
- Intel Corporation
- Jaume Abella
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory apparatuses with low supply voltages
- Patent number 8,477,558
- Issue date Jul 2, 2013
- Intel Corporation
- Jaume Abella
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Detecting soft errors via selective re-execution
- Patent number 8,402,310
- Issue date Mar 19, 2013
- Intel Corporation
- Xavier Vera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Protecting data storage structures from intermittent errors
- Patent number 8,352,812
- Issue date Jan 8, 2013
- Intel Corporation
- Xavier Vera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Disabling cache portions during low voltage operations
- Patent number 8,291,168
- Issue date Oct 16, 2012
- Intel Corporation
- Christopher Wilkerson
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Dynamically estimating lifetime of a semiconductor device
- Patent number 8,151,094
- Issue date Apr 3, 2012
- Intel Corporation
- Xavier Vera
- G01 - MEASURING TESTING
Information Patent Grant
Disabling cache portions during low voltage operations
- Patent number 8,103,830
- Issue date Jan 24, 2012
- Intel Corporation
- Christopher Wilkerson
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Detecting soft errors via selective re-execution
- Patent number 8,090,996
- Issue date Jan 3, 2012
- Intel Corporation
- Xavier Vera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Enhancing reliability of a many-core processor
- Patent number 8,074,110
- Issue date Dec 6, 2011
- Intel Corporation
- Xavier Vera
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
On-line testing for decode logic
- Patent number 8,069,376
- Issue date Nov 29, 2011
- Intel Corporation
- Pedro Chaparro Monferrer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Correcting intermittent errors in data storage structures
- Patent number 7,747,913
- Issue date Jun 29, 2010
- Intel Corporation
- Jaume Abella
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Selectively protecting a register file
- Patent number 7,689,804
- Issue date Mar 30, 2010
- Intel Corporation
- Xavier Vera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clustered variations-aware architecture
- Patent number 7,600,145
- Issue date Oct 6, 2009
- Intel Corporation
- Xavier Vera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory content inverting to minimize NTBI effects
- Patent number 7,577,015
- Issue date Aug 18, 2009
- Intel Corporation
- Jaume Abella
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reducing the soft error vulnerability of stored data
- Patent number 7,558,992
- Issue date Jul 7, 2009
- Intel Corporation
- Oguz Ergin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
NBTI-resilient memory cells with NAND gates
- Patent number 7,447,054
- Issue date Nov 4, 2008
- Intel Corporation
- Jaume Abella
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
DISABLING CACHE PORTIONS DURING LOW VOLTAGE OPERATIONS
- Publication number 20180060239
- Publication date Mar 1, 2018
- Intel Corporation
- CHRISTOPHER WILKERSON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRAFFIC CONTROL ON AN ON-CHIP NETWORK
- Publication number 20170201459
- Publication date Jul 13, 2017
- Intel Corporation
- MATTEO MONCHIERO
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
REGISTER ERROR PROTECTION THROUGH BINARY TRANSLATION
- Publication number 20160342495
- Publication date Nov 24, 2016
- Intel Corporation
- XAVIER VERA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VULNERABILITY ESTIMATION FOR CACHE MEMORY
- Publication number 20140281740
- Publication date Sep 18, 2014
- Intel Corporation
- Javier Carretero Casado
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INCREASED ERROR CORRECTION FOR CACHE MEMORIES THROUGH ADAPTIVE REPL...
- Publication number 20140281261
- Publication date Sep 18, 2014
- Intel Corporation
- Xavier Vera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SELECTIVE PROVISION OF ERROR CORRECTION FOR MEMORY
- Publication number 20140258805
- Publication date Sep 11, 2014
- Javier Carretero Casado
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRACKING DISTRIBUTED EXECUTION ON ON-CHIP MULTINODE NETWORKS WITHOU...
- Publication number 20140237018
- Publication date Aug 21, 2014
- Matteo Monchiero
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BANKING OF RELIABILITY METRICS
- Publication number 20140189439
- Publication date Jul 3, 2014
- Enric Herrero Abellanas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FAILURE RATE BASED CONTROL OF PROCESSORS
- Publication number 20140189696
- Publication date Jul 3, 2014
- Enric H. Abellanas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DISABLING CACHE PORTIONS DURING LOW VOLTAGE OPERATIONS
- Publication number 20140108733
- Publication date Apr 17, 2014
- Christopher Wilkerson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RECOVERING FROM DATA ERRORS USING IMPLICIT REDUNDANCY
- Publication number 20140089593
- Publication date Mar 27, 2014
- Xavier Vera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONTENT-AWARE CACHES FOR RELIABILITY
- Publication number 20140019823
- Publication date Jan 16, 2014
- Tanausu Ramirez
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRAFFIC CONTROL ON AN ON-CHIP NETWORK
- Publication number 20140010079
- Publication date Jan 9, 2014
- Matteo Monchiero
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FAULT-AWARE MAPPING FOR SHARED LAST LEVEL CACHE (LLC)
- Publication number 20140006849
- Publication date Jan 2, 2014
- Tanausu Ramirez
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REGISTER ERROR PROTECTION THROUGH BINARY TRANSLATION
- Publication number 20130318401
- Publication date Nov 28, 2013
- Xavier Vera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DISABLING CACHE PORTIONS DURING LOW VOLTAGE OPERATIONS
- Publication number 20120110266
- Publication date May 3, 2012
- Christopher Wilkerson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Detecting Soft Errors Via Selective Re-Execution
- Publication number 20120047398
- Publication date Feb 23, 2012
- Xavier Vera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ON-LINE TESTING FOR DECODE LOGIC
- Publication number 20100299507
- Publication date Nov 25, 2010
- Pedro Chaparro Monferrer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY APPARATUSES WITH LOW SUPPLY VOLTAGES
- Publication number 20100115224
- Publication date May 6, 2010
- Jaume Abella
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DISABLING CACHE PORTIONS DURING LOW VOLTAGE OPERATIONS
- Publication number 20100082905
- Publication date Apr 1, 2010
- Christopher Wilkerson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Dynamically Estimating Lifetime of a Semiconductor Device
- Publication number 20090287909
- Publication date Nov 19, 2009
- Xavier Vera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Mechanism for soft error detection and recovery in issue queues
- Publication number 20090150653
- Publication date Jun 11, 2009
- Pedro Chaparro Monferrer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CAPACITY REGISTER FILE
- Publication number 20090150649
- Publication date Jun 11, 2009
- Jaume Abella
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Reducing Aging Effect On Registers
- Publication number 20090150656
- Publication date Jun 11, 2009
- Jaume Abella
- G11 - INFORMATION STORAGE
Information Patent Application
Detecting Soft Errors Via Selective Re-Execution
- Publication number 20090113240
- Publication date Apr 30, 2009
- Xavier Vera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Enhancing Reliability of a Many-Core Processor
- Publication number 20090094481
- Publication date Apr 9, 2009
- Xavier Vera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CORRECTING INTERMITTENT ERRORS IN DATA STORAGE STRUCTURES
- Publication number 20090037781
- Publication date Feb 5, 2009
- Jaume Abella
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROTECTING DATA STORAGE STRUCTURES FROM INTERMITTENT ERRORS
- Publication number 20090037783
- Publication date Feb 5, 2009
- Xavier Vera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory content inverting to minimize NTBI effects
- Publication number 20080244182
- Publication date Oct 2, 2008
- Jaume Abella
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Selectively protecting a register file
- Publication number 20080155375
- Publication date Jun 26, 2008
- Xavier Vera
- G06 - COMPUTING CALCULATING COUNTING

Xavier Vera

Person

Patents Grantslast 30 patents

Disabling cache portions during low voltage operations

Capacity register file

Disabling cache portions during low voltage operations

Enforcing different operational configurations for different tasks...

Traffic control on an on-chip network

Register error protection through binary translation

Fault-aware mapping for shared last level cache (LLC)

Increased error correction for cache memories through adaptive repl...

Recovering from data errors using implicit redundancy

Content-aware caches for reliability

Vulnerability estimation for cache memory

Selective provision of error correction for memory

Banking of reliability metrics

Reducing aging effect on registers

Memory apparatuses with low supply voltages

Detecting soft errors via selective re-execution

Protecting data storage structures from intermittent errors

Disabling cache portions during low voltage operations

Dynamically estimating lifetime of a semiconductor device

Disabling cache portions during low voltage operations

Detecting soft errors via selective re-execution

Enhancing reliability of a many-core processor

On-line testing for decode logic

Correcting intermittent errors in data storage structures

Selectively protecting a register file

Clustered variations-aware architecture

Memory content inverting to minimize NTBI effects

Reducing the soft error vulnerability of stored data

NBTI-resilient memory cells with NAND gates

Patents Applicationslast 30 patents

DISABLING CACHE PORTIONS DURING LOW VOLTAGE OPERATIONS

TRAFFIC CONTROL ON AN ON-CHIP NETWORK

REGISTER ERROR PROTECTION THROUGH BINARY TRANSLATION

VULNERABILITY ESTIMATION FOR CACHE MEMORY

INCREASED ERROR CORRECTION FOR CACHE MEMORIES THROUGH ADAPTIVE REPL...

SELECTIVE PROVISION OF ERROR CORRECTION FOR MEMORY

TRACKING DISTRIBUTED EXECUTION ON ON-CHIP MULTINODE NETWORKS WITHOU...

BANKING OF RELIABILITY METRICS

FAILURE RATE BASED CONTROL OF PROCESSORS

DISABLING CACHE PORTIONS DURING LOW VOLTAGE OPERATIONS

RECOVERING FROM DATA ERRORS USING IMPLICIT REDUNDANCY

CONTENT-AWARE CACHES FOR RELIABILITY

TRAFFIC CONTROL ON AN ON-CHIP NETWORK

FAULT-AWARE MAPPING FOR SHARED LAST LEVEL CACHE (LLC)

REGISTER ERROR PROTECTION THROUGH BINARY TRANSLATION

DISABLING CACHE PORTIONS DURING LOW VOLTAGE OPERATIONS

Detecting Soft Errors Via Selective Re-Execution

ON-LINE TESTING FOR DECODE LOGIC

MEMORY APPARATUSES WITH LOW SUPPLY VOLTAGES

DISABLING CACHE PORTIONS DURING LOW VOLTAGE OPERATIONS

Dynamically Estimating Lifetime of a Semiconductor Device

Mechanism for soft error detection and recovery in issue queues

CAPACITY REGISTER FILE

Reducing Aging Effect On Registers

Detecting Soft Errors Via Selective Re-Execution

Enhancing Reliability of a Many-Core Processor

CORRECTING INTERMITTENT ERRORS IN DATA STORAGE STRUCTURES

PROTECTING DATA STORAGE STRUCTURES FROM INTERMITTENT ERRORS

Memory content inverting to minimize NTBI effects

Selectively protecting a register file