Xi-Wei Lin

Person

Fremont, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Self-limiting manufacturing techniques to prevent electrical shorts...
- Patent number 12,080,608
- Issue date Sep 3, 2024
- Synopsys, Inc.
- Xi-Wei Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Power routing for 2.5D or 3D integrated circuits including a buried...
- Patent number 11,984,384
- Issue date May 14, 2024
- Synopsys, Inc.
- Xi-Wei Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Forming a wrap-around contact to connect a source or drain epitaxia...
- Patent number 11,915,984
- Issue date Feb 27, 2024
- Synopsys, Inc.
- Xi-Wei Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fin patterning to reduce fin collapse and transistor leakage
- Patent number 11,776,816
- Issue date Oct 3, 2023
- Synopsys, Inc.
- Victor Moroz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Epitaxial growth of source and drain materials in a complementary f...
- Patent number 11,742,247
- Issue date Aug 29, 2023
- Synopsys, Inc.
- Xi-Wei Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fabrication technique for forming ultra-high density integrated cir...
- Patent number 11,710,634
- Issue date Jul 25, 2023
- Synopsys, Inc.
- Xi-Wei Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Automated resistance and capacitance extraction and netlist generat...
- Patent number 10,482,212
- Issue date Nov 19, 2019
- Synopsys, Inc.
- Zudian Qin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pre-silicon design rule evaluation
- Patent number 10,311,200
- Issue date Jun 4, 2019
- Synopsys, Inc.
- Victor Moroz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods for fabricating high-density integrated circuit devices
- Patent number 9,547,740
- Issue date Jan 17, 2017
- Synopsys, Inc.
- Victor Moroz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Chip cross-section identification and rendering analysis
- Patent number 9,471,745
- Issue date Oct 18, 2016
- Synopsys, Inc.
- Xi-Wei Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
SRAM layouts
- Patent number 9,418,189
- Issue date Aug 16, 2016
- Synopsys, Inc.
- Xi-Wei Lin
- G11 - INFORMATION STORAGE
Information Patent Grant
Increasing Ion/Ioff ratio in FinFETs and nano-wires
- Patent number 9,379,018
- Issue date Jun 28, 2016
- Synopsys, Inc.
- Munkang Choi
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Chip cross-section identification and rendering during failure anal...
- Patent number 9,147,027
- Issue date Sep 29, 2015
- Synopsys, Inc.
- Xi-Wei Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
SRAM layouts
- Patent number 8,964,453
- Issue date Feb 24, 2015
- Synopsys, Inc.
- Xi-Wei Lin
- G11 - INFORMATION STORAGE
Information Patent Grant
Boosting transistor performance with non-rectangular channels
- Patent number 8,869,078
- Issue date Oct 21, 2014
- Synopsys, Inc.
- Victor Moroz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Increasing ION /IOFF ratio in FinFETs and nano-wires
- Patent number 8,847,324
- Issue date Sep 30, 2014
- Synopsys, Inc.
- Munkang Choi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Modeling mechanical behavior with layout-dependent material properties
- Patent number 8,776,005
- Issue date Jul 8, 2014
- Synopsys, Inc.
- Xiaopeng Xu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Boosting transistor performance with non-rectangular channels
- Patent number 8,701,054
- Issue date Apr 15, 2014
- Synopsys, Inc.
- Victor Moroz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Filler cells for design optimization in a place-and-route system
- Patent number 8,694,942
- Issue date Apr 8, 2014
- Synopsys, Inc.
- Xi-Wei Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Elevation of transistor channels to reduce impact of shallow trench...
- Patent number 8,686,512
- Issue date Apr 1, 2014
- Synopsys, Inc.
- Victor Moroz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Filler cells for design optimization in a place-and-route system
- Patent number 8,504,969
- Issue date Aug 6, 2013
- Synopsys, Inc.
- Xi-Wei Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for compensation of process-induced performance variation in...
- Patent number 8,219,961
- Issue date Jul 10, 2012
- Synopsys, Inc.
- Victor Moroz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of correlating silicon stress to device instance parameters...
- Patent number 8,086,990
- Issue date Dec 27, 2011
- Synopsys, Inc.
- Xi-Wei Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Stress-managed revision of integrated circuit layouts
- Patent number 8,069,430
- Issue date Nov 29, 2011
- Synopsys, Inc.
- Victor Moroz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Elevation of transistor channels to reduce impact of shallow trench...
- Patent number 8,035,168
- Issue date Oct 11, 2011
- Synopsys, Inc.
- Victor Moroz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for compensation of process-induced performance variation in...
- Patent number 7,949,985
- Issue date May 24, 2011
- Synopsys, Inc.
- Victor Moroz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for generating a layout for a transistor
- Patent number 7,926,018
- Issue date Apr 12, 2011
- Synopsys, Inc.
- Victor Moroz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Minimizing effects of interconnect variations in integrated circuit...
- Patent number 7,908,573
- Issue date Mar 15, 2011
- Synopsys, Inc.
- Xi-Wei Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Managing integrated circuit stress using dummy diffusion regions
- Patent number 7,897,479
- Issue date Mar 1, 2011
- Synopsys, Inc.
- Xi-Wei Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Filler cells for design optimization in a place-and-route system
- Patent number 7,895,548
- Issue date Feb 22, 2011
- Synopsys, Inc.
- Xi Wei Lin
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Power Routing for 2.5D or 3D Integrated Circuits Including a Buried...
- Publication number 20240258206
- Publication date Aug 1, 2024
- Synopsys, Inc.
- Xi-Wei LIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FORMING A WRAP-AROUND CONTACT TO CONNECT A SOURCE OR DRAIN EPITAXIA...
- Publication number 20230163032
- Publication date May 25, 2023
- Synopsys, Inc.
- Xi-Wei LIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FABRICATION TECHNIQUE FOR FORMING ULTRA-HIGH DENSITY INTEGRATED CIR...
- Publication number 20230154751
- Publication date May 18, 2023
- Synopsys, Inc.
- XI-WEI LIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
POWER ROUTING FOR 2.5D OR 3D INTEGRATED CIRCUITS
- Publication number 20230074159
- Publication date Mar 9, 2023
- Synopsys, Inc.
- Xi-Wei LIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FIN PATTERNING TO REDUCE FIN COLLAPSE AND TRANSISTOR LEAKAGE
- Publication number 20220172953
- Publication date Jun 2, 2022
- Synopsys, Inc.
- VICTOR MOROZ
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EPITAXIAL GROWTH OF SOURCE AND DRAIN MATERIALS IN A COMPLEMENTARY F...
- Publication number 20220020646
- Publication date Jan 20, 2022
- Synopsys, Inc.
- Xi-Wei LIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-LIMITING MANUFACTURING TECHNIQUES TO PREVENT ELECTRICAL SHORTS...
- Publication number 20220020647
- Publication date Jan 20, 2022
- Synopsys, Inc.
- Xi-Wei LIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Automated Resistance and Capacitance Extraction and Netlist Generat...
- Publication number 20180239857
- Publication date Aug 23, 2018
- Synopsys, Inc.
- Zudian Qin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Pre-Silicon Design Rule Evaluation
- Publication number 20170039308
- Publication date Feb 9, 2017
- Synopsys, Inc.
- Victor Moroz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CHIP CROSS-SECTION IDENTIFICATION AND RENDERING ANALYSIS
- Publication number 20160019331
- Publication date Jan 21, 2016
- Synopsys, Inc.
- Xi-Wei Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and System for Generating a Circuit Design, Method for Calib...
- Publication number 20150356232
- Publication date Dec 10, 2015
- Synopsys, Inc.
- Lars Henning Bomholt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS FOR FABRICATING HIGH-DENSITY INTEGRATED CIRCUIT DEVICES
- Publication number 20150143306
- Publication date May 21, 2015
- Synopsys, Inc.
- VICTOR MOROZ
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SRAM LAYOUTS
- Publication number 20150113492
- Publication date Apr 23, 2015
- Synopsys, Inc.
- XI-WEI LIN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INCREASING ION/IOFF RATIO IN FINFETS AND NANO-WIRES
- Publication number 20150041921
- Publication date Feb 12, 2015
- Synopsys, Inc.
- Munkang Choi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CHIP CROSS-SECTION IDENTIFICATION AND RENDERING DURING FAILURE ANAL...
- Publication number 20150007121
- Publication date Jan 1, 2015
- Synopsys, Inc.
- Xi-Wei Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BOOSTING TRANSISTOR PERFORMANCE WITH NON-RECTANGULAR CHANNELS
- Publication number 20140223395
- Publication date Aug 7, 2014
- Synopsys, Inc.
- Victor Moroz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MODELING MECHANICAL BEHAVIOR WITH LAYOUT-DEPENDENT MATERIAL PROPERTIES
- Publication number 20140208280
- Publication date Jul 24, 2014
- Synopsys, Inc.
- Xiaopeng Xu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INCREASING ION/IOFF RATIO IN FINFETS AND NANO-WIRES
- Publication number 20140167174
- Publication date Jun 19, 2014
- Munkang Choi
- B82 - NANO-TECHNOLOGY
Information Patent Application
SRAM LAYOUTS
- Publication number 20140003133
- Publication date Jan 2, 2014
- Synopsys, Inc.
- XI-WEI LIN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FILLER CELLS FOR DESIGN OPTIMIZATION IN A PLACE-AND-ROUTE SYSTEM
- Publication number 20130332893
- Publication date Dec 12, 2013
- Xi-Wei Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS FOR FABRICATING HIGH-DENSITY INTEGRATED CIRCUIT DEVICES
- Publication number 20120280354
- Publication date Nov 8, 2012
- Synopsys, Inc.
- VICTOR MOROZ
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BOOSTING TRANSISTOR PERFORMANCE WITH NON-RECTANGULAR CHANNELS
- Publication number 20120011479
- Publication date Jan 12, 2012
- Synopsys, Inc.
- Victor Moroz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ELEVATION OF TRANSISTOR CHANNELS TO REDUCE IMPACT OF SHALLOW TRENCH...
- Publication number 20110309453
- Publication date Dec 22, 2011
- Victor Moroz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for Compensation of Process-Induced Performance Variation in...
- Publication number 20110219351
- Publication date Sep 8, 2011
- Synopsys, Inc.
- Victor Moroz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FILLER CELLS FOR DESIGN OPTIMIZATION IN A PLACE-AND-ROUTE SYSTEM
- Publication number 20110078639
- Publication date Mar 31, 2011
- Synopsys, Inc.
- Xi-Wei Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BOOSTING TRANSISTOR PERFORMANCE WITH NON-RECTANGULAR CHANNELS
- Publication number 20100187609
- Publication date Jul 29, 2010
- Synopsys, Inc.
- Victor Moroz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Managing Integrated Circuit Stress Using Stress Adjustment Trenches
- Publication number 20100019317
- Publication date Jan 28, 2010
- Synopsys, Inc.
- Victor Moroz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Minimizing Effects of Interconnect Variations in Integrated Circuit...
- Publication number 20090319960
- Publication date Dec 24, 2009
- Synopsys, Inc.
- Xi-Wei Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STRESS-MANAGED REVISION OF INTEGRATED CIRCUIT LAYOUTS
- Publication number 20090313595
- Publication date Dec 17, 2009
- Synopsys, Inc.
- Victor Moroz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD OF CORRELATING SILICON STRESS TO DEVICE INSTANCE PARAMETERS...
- Publication number 20090217217
- Publication date Aug 27, 2009
- Synopsys, Inc.
- Xi-Wei Lin
- G06 - COMPUTING CALCULATING COUNTING

Person

Patents Grantslast 30 patents

Self-limiting manufacturing techniques to prevent electrical shorts...

Power routing for 2.5D or 3D integrated circuits including a buried...

Forming a wrap-around contact to connect a source or drain epitaxia...

Fin patterning to reduce fin collapse and transistor leakage

Epitaxial growth of source and drain materials in a complementary f...

Fabrication technique for forming ultra-high density integrated cir...

Automated resistance and capacitance extraction and netlist generat...

Pre-silicon design rule evaluation

Methods for fabricating high-density integrated circuit devices

Chip cross-section identification and rendering analysis

SRAM layouts

Increasing Ion/Ioff ratio in FinFETs and nano-wires

Chip cross-section identification and rendering during failure anal...

SRAM layouts

Boosting transistor performance with non-rectangular channels

Increasing ION /IOFF ratio in FinFETs and nano-wires

Modeling mechanical behavior with layout-dependent material properties

Boosting transistor performance with non-rectangular channels

Filler cells for design optimization in a place-and-route system

Elevation of transistor channels to reduce impact of shallow trench...

Filler cells for design optimization in a place-and-route system

Method for compensation of process-induced performance variation in...

Method of correlating silicon stress to device instance parameters...

Stress-managed revision of integrated circuit layouts

Elevation of transistor channels to reduce impact of shallow trench...

Method for compensation of process-induced performance variation in...

Method and apparatus for generating a layout for a transistor

Minimizing effects of interconnect variations in integrated circuit...

Managing integrated circuit stress using dummy diffusion regions

Filler cells for design optimization in a place-and-route system

Patents Applicationslast 30 patents

Power Routing for 2.5D or 3D Integrated Circuits Including a Buried...

FORMING A WRAP-AROUND CONTACT TO CONNECT A SOURCE OR DRAIN EPITAXIA...

FABRICATION TECHNIQUE FOR FORMING ULTRA-HIGH DENSITY INTEGRATED CIR...

POWER ROUTING FOR 2.5D OR 3D INTEGRATED CIRCUITS

FIN PATTERNING TO REDUCE FIN COLLAPSE AND TRANSISTOR LEAKAGE

EPITAXIAL GROWTH OF SOURCE AND DRAIN MATERIALS IN A COMPLEMENTARY F...

SELF-LIMITING MANUFACTURING TECHNIQUES TO PREVENT ELECTRICAL SHORTS...

Automated Resistance and Capacitance Extraction and Netlist Generat...

Pre-Silicon Design Rule Evaluation

CHIP CROSS-SECTION IDENTIFICATION AND RENDERING ANALYSIS

Method and System for Generating a Circuit Design, Method for Calib...

METHODS FOR FABRICATING HIGH-DENSITY INTEGRATED CIRCUIT DEVICES

SRAM LAYOUTS

INCREASING ION/IOFF RATIO IN FINFETS AND NANO-WIRES

CHIP CROSS-SECTION IDENTIFICATION AND RENDERING DURING FAILURE ANAL...

BOOSTING TRANSISTOR PERFORMANCE WITH NON-RECTANGULAR CHANNELS

MODELING MECHANICAL BEHAVIOR WITH LAYOUT-DEPENDENT MATERIAL PROPERTIES

INCREASING ION/IOFF RATIO IN FINFETS AND NANO-WIRES

SRAM LAYOUTS

FILLER CELLS FOR DESIGN OPTIMIZATION IN A PLACE-AND-ROUTE SYSTEM

METHODS FOR FABRICATING HIGH-DENSITY INTEGRATED CIRCUIT DEVICES

BOOSTING TRANSISTOR PERFORMANCE WITH NON-RECTANGULAR CHANNELS

ELEVATION OF TRANSISTOR CHANNELS TO REDUCE IMPACT OF SHALLOW TRENCH...

Method for Compensation of Process-Induced Performance Variation in...

FILLER CELLS FOR DESIGN OPTIMIZATION IN A PLACE-AND-ROUTE SYSTEM

BOOSTING TRANSISTOR PERFORMANCE WITH NON-RECTANGULAR CHANNELS

Managing Integrated Circuit Stress Using Stress Adjustment Trenches

Minimizing Effects of Interconnect Variations in Integrated Circuit...

STRESS-MANAGED REVISION OF INTEGRATED CIRCUIT LAYOUTS

METHOD OF CORRELATING SILICON STRESS TO DEVICE INSTANCE PARAMETERS...