Xi ZHANG

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Full adder cell with improved power efficiency
- Patent number 11,294,631
- Issue date Apr 5, 2022
- NVIDIA Corp.
- Ilyas Elkin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Full adder cell with improved power efficiency
- Patent number 11,169,779
- Issue date Nov 9, 2021
- NVIDIA Corp.
- Ilyas Elkin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low power flip-flop element with gated clock
- Patent number 10,931,266
- Issue date Feb 23, 2021
- NVIDIA Corporation
- Ilyas Elkin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Mixed threshold flip-flop element to mitigate hold time penalty due...
- Patent number 10,181,842
- Issue date Jan 15, 2019
- NVIDIA Corporation
- Ge Yang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Mitigating external influences on long signal lines
- Patent number 9,842,631
- Issue date Dec 12, 2017
- NVIDIA Corporation
- Ge Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
SRAM core cell design with write assist
- Patent number 9,542,992
- Issue date Jan 10, 2017
- NVIDIA Corporation
- Hwong-Kwo Lin
- G11 - INFORMATION STORAGE
Information Patent Grant
Low clocking power flip-flop
- Patent number 9,525,401
- Issue date Dec 20, 2016
- NVIDIA Corporation
- Xi Zhang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low tau synchronizer flip-flop with dual loop feedback approach to...
- Patent number 9,219,480
- Issue date Dec 22, 2015
- NVIDIA Corporation
- Hwong-Kwo Lin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Flip-flop circuit having a reduced hold time requirement for a scan...
- Patent number 9,110,141
- Issue date Aug 18, 2015
- NVIDIA Corporation
- Hwong-Kwo Lin
- G01 - MEASURING TESTING
Information Patent Grant
Low power, single-rail level shifters employing power down signal f...
- Patent number 9,071,240
- Issue date Jun 30, 2015
- NVIDIA Corporation
- Hank Lin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Small area low power data retention flop
- Patent number 8,988,123
- Issue date Mar 24, 2015
- NVIDIA Corporation
- Ge Yang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dual flip-flop circuit
- Patent number 8,866,528
- Issue date Oct 21, 2014
- NVIDIA Corporation
- Hwong-Kwo Lin
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
FULL ADDER CELL WITH IMPROVED POWER EFFICIENCY
- Publication number 20210124558
- Publication date Apr 29, 2021
- NVIDIA Corp.
- Ilyas Elkin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FULL ADDER CELL WITH IMPROVED POWER EFFICIENCY
- Publication number 20210124559
- Publication date Apr 29, 2021
- NVIDIA Corp.
- Ilyas Elkin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MIXED THRESHOLD FLIP-FLOP ELEMENT TO MITIGATE HOLD TIME PENALTY DUE...
- Publication number 20170141768
- Publication date May 18, 2017
- NVIDIA Corporation
- Ge YANG
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
LOW CLOCKING POWER FLIP-FLOP
- Publication number 20160269002
- Publication date Sep 15, 2016
- NVIDIA Corporation
- Xi Zhang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
LOW POWER FLIP-FLOP ELEMENT WITH GATED CLOCK
- Publication number 20160043706
- Publication date Feb 11, 2016
- NVIDIA Corporation
- Ilyas ELKIN
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
LOW TAU SYNCHRONIZER FLIP-FLOP WITH DUAL LOOP FEEDBACK APPROACH TO...
- Publication number 20150222266
- Publication date Aug 6, 2015
- NVIDIA Corporation
- Hwong-Kwo Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SRAM CORE CELL DESIGN WITH WRITE ASSIST
- Publication number 20140313817
- Publication date Oct 23, 2014
- NVIDIA Corporation
- Hwong-Kwo LIN
- G11 - INFORMATION STORAGE
Information Patent Application
MITIGATING EXTERNAL INFLUENCES ON LONG SIGNAL LINES
- Publication number 20140169108
- Publication date Jun 19, 2014
- NVIDIA Corporation
- Ge Yang
- G11 - INFORMATION STORAGE
Information Patent Application
SMALL AREA LOW POWER DATA RETENTION FLOP
- Publication number 20140167828
- Publication date Jun 19, 2014
- NVIDIA Corporation
- Ge Yang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DUAL FLIP-FLOP CIRCUIT
- Publication number 20140125377
- Publication date May 8, 2014
- NVIDIA Corporation
- Hwong-Kwo Lin
- G01 - MEASURING TESTING
Information Patent Application
FLIP-FLOP CIRCUIT HAVING A REDUCED HOLD TIME REQUIREMENT FOR A SCAN...
- Publication number 20140129887
- Publication date May 8, 2014
- NVIDIA Corporation
- Hwong-Kwo Lin
- G01 - MEASURING TESTING
Information Patent Application
LOW POWER, SINGLE-RAIL LEVEL SHIFTERS EMPLOYING POWER DOWN SIGNAL F...
- Publication number 20140084984
- Publication date Mar 27, 2014
- NVIDIA Corporation
- Hank Lin
- H03 - BASIC ELECTRONIC CIRCUITRY

Person

Patents Grantslast 30 patents

Full adder cell with improved power efficiency

Full adder cell with improved power efficiency

Low power flip-flop element with gated clock

Mixed threshold flip-flop element to mitigate hold time penalty due...

Mitigating external influences on long signal lines

SRAM core cell design with write assist

Low clocking power flip-flop

Low tau synchronizer flip-flop with dual loop feedback approach to...

Flip-flop circuit having a reduced hold time requirement for a scan...

Low power, single-rail level shifters employing power down signal f...

Small area low power data retention flop

Dual flip-flop circuit

Patents Applicationslast 30 patents

FULL ADDER CELL WITH IMPROVED POWER EFFICIENCY

FULL ADDER CELL WITH IMPROVED POWER EFFICIENCY

MIXED THRESHOLD FLIP-FLOP ELEMENT TO MITIGATE HOLD TIME PENALTY DUE...

LOW CLOCKING POWER FLIP-FLOP

LOW POWER FLIP-FLOP ELEMENT WITH GATED CLOCK

LOW TAU SYNCHRONIZER FLIP-FLOP WITH DUAL LOOP FEEDBACK APPROACH TO...

SRAM CORE CELL DESIGN WITH WRITE ASSIST

MITIGATING EXTERNAL INFLUENCES ON LONG SIGNAL LINES

SMALL AREA LOW POWER DATA RETENTION FLOP

DUAL FLIP-FLOP CIRCUIT

FLIP-FLOP CIRCUIT HAVING A REDUCED HOLD TIME REQUIREMENT FOR A SCAN...

LOW POWER, SINGLE-RAIL LEVEL SHIFTERS EMPLOYING POWER DOWN SIGNAL F...