Xiang Yang

Person

Milpitas, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Three-bit-per-cell programming using a four-bit-per-cell programmin...
- Patent number 12,254,931
- Issue date Mar 18, 2025
- SanDisk Technologies, Inc.
- Xiang Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
In-place write techniques without erase in a memory device
- Patent number 12,243,591
- Issue date Mar 4, 2025
- SanDisk Technologies, Inc.
- Xiang Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Low power read method and a memory device capable thereof
- Patent number 12,243,593
- Issue date Mar 4, 2025
- SanDisk Technologies, Inc.
- Xiang Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Hole channel pre-charge to enable large-volume in-place data saniti...
- Patent number 12,229,415
- Issue date Feb 18, 2025
- SANDISK TECHNOLOGIES LLC
- Wei Cao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache processes with adaptive dynamic start voltage calculation for...
- Patent number 12,224,019
- Issue date Feb 11, 2025
- Intel Corporation
- Xiang Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
MLC programming techniques in a memory device
- Patent number 12,205,654
- Issue date Jan 21, 2025
- SanDisk Technologies LLC
- Xiang Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Hybrid smart verify for QLC/TLC die
- Patent number 12,205,657
- Issue date Jan 21, 2025
- SANDISK TECHNOLOGIES LLC
- Xiang Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Pump skip for fast single-level cell non-volatile memory
- Patent number 12,198,765
- Issue date Jan 14, 2025
- SanDisk Technologies LLC
- Xiang Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-volatile memory with different word line to word line pitches
- Patent number 12,176,037
- Issue date Dec 24, 2024
- SanDisk Technologies LLC
- Xiang Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Erase method for non-volatile memory with multiple tiers
- Patent number 12,148,478
- Issue date Nov 19, 2024
- SANDISK TECHNOLOGIES LLC
- Xiang Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Low power multi-level cell (MLC) programming in non-volatile memory...
- Patent number 12,142,315
- Issue date Nov 12, 2024
- SanDisk Technologies LLC
- Xiang Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
High speed multi-level cell (MLC) programming in non-volatile memor...
- Patent number 12,112,800
- Issue date Oct 8, 2024
- SanDisk Technologies LLC
- Xiang Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-volatile memory with early dummy word line ramp down after prec...
- Patent number 12,112,812
- Issue date Oct 8, 2024
- SANDISK TECHNOLOGIES LLC
- Jiacen Guo
- G11 - INFORMATION STORAGE
Information Patent Grant
Bundle multiple timing parameters for fast SLC programming
- Patent number 12,079,496
- Issue date Sep 3, 2024
- SanDisk Technologies LLC
- Chin-Yi Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory apparatus and method of operation using state dependent stro...
- Patent number 12,057,175
- Issue date Aug 6, 2024
- SanDisk Technologies LLC
- Chin-Yi Chen
- G11 - INFORMATION STORAGE
Information Patent Grant
Secondary cross-coupling effect in memory apparatus with semicircle...
- Patent number 12,057,166
- Issue date Aug 6, 2024
- SanDisk Technologies LLC
- Xiang Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
In-place write techniques without erase in a memory device
- Patent number 12,045,511
- Issue date Jul 23, 2024
- SanDisk Technologies LLC
- Xiang Yang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pre-position dummy word line to facilitate write erase capability o...
- Patent number 12,046,305
- Issue date Jul 23, 2024
- SanDisk Technologies LLC
- Xiang Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Edge word line concurrent programming with verify for memory appara...
- Patent number 12,046,302
- Issue date Jul 23, 2024
- SanDisk Technologies LLC
- Xiang Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Adaptive semi-circle select gate bias
- Patent number 12,014,785
- Issue date Jun 18, 2024
- SanDisk Technologies LLC
- Xiang Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamic word line reconfiguration for NAND structure
- Patent number 11,990,185
- Issue date May 21, 2024
- SANDISK TECHNOLOGIES LLC
- Xiang Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Recovery pulses to counter cumulative read disturb
- Patent number 11,972,808
- Issue date Apr 30, 2024
- SanDisk Technologies, LLC
- Abhijith Prakash
- G11 - INFORMATION STORAGE
Information Patent Grant
Systems and methods for adapting sense time
- Patent number 11,972,813
- Issue date Apr 30, 2024
- SanDisk Technologies, LLC
- Jiacen Guo
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-volatile memory with tier-wise ramp down after program-verify
- Patent number 11,972,820
- Issue date Apr 30, 2024
- SANDISK TECHNOLOGIES LLC
- Jiacen Guo
- G11 - INFORMATION STORAGE
Information Patent Grant
Read techniques to reduce read errors in a memory device
- Patent number 11,972,806
- Issue date Apr 30, 2024
- SanDisk Technologies, LLC
- Jiacen Guo
- G11 - INFORMATION STORAGE
Information Patent Grant
Refresh frequency-dependent system-level trimming of verify level o...
- Patent number 11,972,818
- Issue date Apr 30, 2024
- SanDisk Technologies, LLC
- Abhijith Prakash
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-volatile memory with one sided phased ramp down after program-v...
- Patent number 11,972,819
- Issue date Apr 30, 2024
- SANDISK TECHNOLOGIES LLC
- Jiacen Guo
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device that is optimized for operation at different temperat...
- Patent number 11,961,573
- Issue date Apr 16, 2024
- SanDisk Technologies, LLC
- Abhijith Prakash
- G11 - INFORMATION STORAGE
Information Patent Grant
Edge word line data retention improvement for memory apparatus with...
- Patent number 11,961,572
- Issue date Apr 16, 2024
- SanDisk Technologies, LLC
- Xiang Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory cell group read with compensation for different programming...
- Patent number 11,955,184
- Issue date Apr 9, 2024
- SanDisk Technologies LLC
- Jiacen Guo
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
WORD LINE ZONE BASED UNSELECT WORD LINE BIAS TO ENABLE SINGLE-SIDE...
- Publication number 20250104774
- Publication date Mar 27, 2025
- Western Digital Technologies, Inc.
- Abhijith Prakash
- G11 - INFORMATION STORAGE
Information Patent Application
THRESHOLD VOLTAGE BUDGET BY EMPLOYING AN OXIDE-NITRIDE PITCH DEPEND...
- Publication number 20250095738
- Publication date Mar 20, 2025
- Western Digital Technologies, Inc.
- Wei Cao
- G11 - INFORMATION STORAGE
Information Patent Application
PROGRAMMING TECHNIQUES TO IMPROVE ERASE STATE UPPER TAILS IN A MEMO...
- Publication number 20250087279
- Publication date Mar 13, 2025
- Western Digital Technologies, Inc.
- Jiacen Guo
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE WITH MULTIPLE PLANE FUNCTIONALITIES
- Publication number 20250060880
- Publication date Feb 20, 2025
- Western Digital Technologies, Inc.
- Xiang Yang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ENERGY EFFICIENT FAST READ IN A MEMORY DEVICE
- Publication number 20250061948
- Publication date Feb 20, 2025
- Western Digital Technologies, Inc.
- Abhijith Prakash
- G11 - INFORMATION STORAGE
Information Patent Application
STATE-DEPENDENT FAIL BIT COUNT CRITERIA FOR MEMORY APPARATUS PROGRA...
- Publication number 20250054556
- Publication date Feb 13, 2025
- Western Digital Technologies, Inc.
- Jiacen Guo
- G11 - INFORMATION STORAGE
Information Patent Application
NON-VOLATILE MEMORY WITH MULTIPLE DATA RESOLUTIONS
- Publication number 20250037783
- Publication date Jan 30, 2025
- Western Digital Technologies, Inc.
- Abhijith Prakash
- G11 - INFORMATION STORAGE
Information Patent Application
EVOLVING BAD BLOCK DETECTION IN NON-VOLATILE MEMORY
- Publication number 20250006285
- Publication date Jan 2, 2025
- Western Digital Technologies, Inc.
- Abhijith Prakash
- G11 - INFORMATION STORAGE
Information Patent Application
ASYMMETRIC PASS VOLTAGE SCHEME FOR NON-VOLATILE MEMORY APPARATUS SI...
- Publication number 20250006244
- Publication date Jan 2, 2025
- Western Digital Technologies, Inc.
- Mohan Vamsi Dunga
- G11 - INFORMATION STORAGE
Information Patent Application
SINGLE BLOCK MODE BLOCK HANDLING FOR SINGLE-SIDE GIDL ERASE
- Publication number 20240427662
- Publication date Dec 26, 2024
- Western Digital Technologies, Inc.
- Abhijith Prakash
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CHANNEL PRE-CHARGE PROCESS FOR MEMORY DEVICES
- Publication number 20240420779
- Publication date Dec 19, 2024
- Western Digital Technologies, Inc.
- Jonathan Huynh
- G11 - INFORMATION STORAGE
Information Patent Application
READ POWER SAVINGS BY TEMPORARILY DISABLING BITLINE VOLTAGE
- Publication number 20240420773
- Publication date Dec 19, 2024
- Western Digital Technologies, Inc.
- Xiang Yang
- G11 - INFORMATION STORAGE
Information Patent Application
OPEN BLOCK DETECTION METHOD USING FOR FIRST AND SECOND TIME PERIOD...
- Publication number 20240420775
- Publication date Dec 19, 2024
- Western Digital Technologies, Inc.
- Albert Chen
- G11 - INFORMATION STORAGE
Information Patent Application
AUTOMATIC BIT LINE VOLTAGE AND BIT LINE VOLTAGE TEMPERATURE COMPENS...
- Publication number 20240411476
- Publication date Dec 12, 2024
- Western Digital Technologies, Inc.
- Albert Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ENABLING SIGNIFICANT SCALING OF WORDLINE SWITCH WITH WORDLINE DEPEN...
- Publication number 20240395330
- Publication date Nov 28, 2024
- Western Digital Technologies, Inc.
- Wei Cao
- G11 - INFORMATION STORAGE
Information Patent Application
WORD LINE DEPENDENT WORD LINE SWITCH DESIGN AND PROGRAMMING TECHNIQUES
- Publication number 20240386930
- Publication date Nov 21, 2024
- Western Digital Technologies, Inc.
- Mohan Vamsi Dunga
- G11 - INFORMATION STORAGE
Information Patent Application
RECONFIGURABLE LINES IN DIFFERENT SUB-BLOCK MODES IN A NAND MEMORY...
- Publication number 20240386971
- Publication date Nov 21, 2024
- Western Digital Technologies, Inc.
- Wei Cao
- G11 - INFORMATION STORAGE
Information Patent Application
POSITIVE SENSING IN LOW POWER OPERATION MODE IN A MEMORY DEVICE
- Publication number 20240386969
- Publication date Nov 21, 2024
- Western Digital Technologies, Inc.
- Abhijith Prakash
- G11 - INFORMATION STORAGE
Information Patent Application
ERASE SATURATION MITIGATION IN NON-VOLATILE MEMORY
- Publication number 20240379175
- Publication date Nov 14, 2024
- Western Digital Technologies, Inc.
- Yi Song
- G11 - INFORMATION STORAGE
Information Patent Application
MULTI-STEP READ PASS VOLTAGE DISCHARGE FOR ICC REDUCTION
- Publication number 20240379170
- Publication date Nov 14, 2024
- Western Digital Technologies, Inc.
- Albert Bor Kai Chen
- G11 - INFORMATION STORAGE
Information Patent Application
ASYMMETRIC VREADK TO REDUCE NEIGHBORING WORD LINE INTERFERENCE IN A...
- Publication number 20240371444
- Publication date Nov 7, 2024
- Western Digital Technologies, Inc.
- Dengtao Zhao
- G11 - INFORMATION STORAGE
Information Patent Application
PLANE AND BLOCK LOCATION DEPENDENT VOLTAGE BIASES IN NAND MEMORY
- Publication number 20240363168
- Publication date Oct 31, 2024
- Western Digital Technologies, Inc.
- Abhijith Prakash
- G11 - INFORMATION STORAGE
Information Patent Application
IN SITU DATA REFRESH WITHOUT ERASE/PROGRAM CYCLES
- Publication number 20240363178
- Publication date Oct 31, 2024
- Western Digital Technologies, Inc.
- Jiacen Guo
- G11 - INFORMATION STORAGE
Information Patent Application
REGULAR TRANSISTOR THRESHOLD VOLTAGE REFRESH FOR SEMI-CIRCLE DRAIN...
- Publication number 20240363177
- Publication date Oct 31, 2024
- Western Digital Technologies, Inc.
- Abhijith Prakash
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NEGATIVE WORD LINE ENABLED PRE-BOOSTING STRATEGY TO IMPROVE NAND PR...
- Publication number 20240355401
- Publication date Oct 24, 2024
- SANDISK TECHNOLOGIES LLC
- Wei Cao
- G11 - INFORMATION STORAGE
Information Patent Application
XOR DATA RECOVERY SCHEMES NONVOLATILE MEMORY DEVICES
- Publication number 20240347122
- Publication date Oct 17, 2024
- SanDisk Technologies LLC
- Xiang Yang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HOLE CHANNEL PRE-CHARGE TO ENABLE LARGE-VOLUME IN-PLACE DATA SANITI...
- Publication number 20240319888
- Publication date Sep 26, 2024
- SANDISK TECHNOLOGIES LLC
- Wei Cao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GENERATION OF QUICK PASS WRITE BIASES IN A MEMORY DEVICE
- Publication number 20240304251
- Publication date Sep 12, 2024
- Western Digital Technologies, Inc.
- Abhijith Prakash
- G11 - INFORMATION STORAGE
Information Patent Application
LOOP DEPENDENT BIT LINE AND READ BIASES IN A MEMORY DEVICE
- Publication number 20240304262
- Publication date Sep 12, 2024
- Western Digital Technologies, Inc.
- Abhijith Prakash
- G11 - INFORMATION STORAGE
Information Patent Application
ACTIVE CURRENT CONSUMPTION SAVE MODE FOR NON-VOLATILE MEMORY USING...
- Publication number 20240296877
- Publication date Sep 5, 2024
- Western Digital Technologies, Inc.
- Ke Zhang
- G11 - INFORMATION STORAGE

Person

Patents Grantslast 30 patents

Three-bit-per-cell programming using a four-bit-per-cell programmin...

In-place write techniques without erase in a memory device

Low power read method and a memory device capable thereof

Hole channel pre-charge to enable large-volume in-place data saniti...

Cache processes with adaptive dynamic start voltage calculation for...

MLC programming techniques in a memory device

Hybrid smart verify for QLC/TLC die

Pump skip for fast single-level cell non-volatile memory

Non-volatile memory with different word line to word line pitches

Erase method for non-volatile memory with multiple tiers

Low power multi-level cell (MLC) programming in non-volatile memory...

High speed multi-level cell (MLC) programming in non-volatile memor...

Non-volatile memory with early dummy word line ramp down after prec...

Bundle multiple timing parameters for fast SLC programming

Memory apparatus and method of operation using state dependent stro...

Secondary cross-coupling effect in memory apparatus with semicircle...

In-place write techniques without erase in a memory device

Pre-position dummy word line to facilitate write erase capability o...

Edge word line concurrent programming with verify for memory appara...

Adaptive semi-circle select gate bias

Dynamic word line reconfiguration for NAND structure

Recovery pulses to counter cumulative read disturb

Systems and methods for adapting sense time

Non-volatile memory with tier-wise ramp down after program-verify

Read techniques to reduce read errors in a memory device

Refresh frequency-dependent system-level trimming of verify level o...

Non-volatile memory with one sided phased ramp down after program-v...

Memory device that is optimized for operation at different temperat...

Edge word line data retention improvement for memory apparatus with...

Memory cell group read with compensation for different programming...

Patents Applicationslast 30 patents

WORD LINE ZONE BASED UNSELECT WORD LINE BIAS TO ENABLE SINGLE-SIDE...

THRESHOLD VOLTAGE BUDGET BY EMPLOYING AN OXIDE-NITRIDE PITCH DEPEND...

PROGRAMMING TECHNIQUES TO IMPROVE ERASE STATE UPPER TAILS IN A MEMO...

MEMORY DEVICE WITH MULTIPLE PLANE FUNCTIONALITIES

ENERGY EFFICIENT FAST READ IN A MEMORY DEVICE

STATE-DEPENDENT FAIL BIT COUNT CRITERIA FOR MEMORY APPARATUS PROGRA...

NON-VOLATILE MEMORY WITH MULTIPLE DATA RESOLUTIONS

EVOLVING BAD BLOCK DETECTION IN NON-VOLATILE MEMORY

ASYMMETRIC PASS VOLTAGE SCHEME FOR NON-VOLATILE MEMORY APPARATUS SI...

SINGLE BLOCK MODE BLOCK HANDLING FOR SINGLE-SIDE GIDL ERASE

CHANNEL PRE-CHARGE PROCESS FOR MEMORY DEVICES

READ POWER SAVINGS BY TEMPORARILY DISABLING BITLINE VOLTAGE

OPEN BLOCK DETECTION METHOD USING FOR FIRST AND SECOND TIME PERIOD...

AUTOMATIC BIT LINE VOLTAGE AND BIT LINE VOLTAGE TEMPERATURE COMPENS...

ENABLING SIGNIFICANT SCALING OF WORDLINE SWITCH WITH WORDLINE DEPEN...

WORD LINE DEPENDENT WORD LINE SWITCH DESIGN AND PROGRAMMING TECHNIQUES

RECONFIGURABLE LINES IN DIFFERENT SUB-BLOCK MODES IN A NAND MEMORY...

POSITIVE SENSING IN LOW POWER OPERATION MODE IN A MEMORY DEVICE

ERASE SATURATION MITIGATION IN NON-VOLATILE MEMORY

MULTI-STEP READ PASS VOLTAGE DISCHARGE FOR ICC REDUCTION

ASYMMETRIC VREADK TO REDUCE NEIGHBORING WORD LINE INTERFERENCE IN A...

PLANE AND BLOCK LOCATION DEPENDENT VOLTAGE BIASES IN NAND MEMORY

IN SITU DATA REFRESH WITHOUT ERASE/PROGRAM CYCLES

REGULAR TRANSISTOR THRESHOLD VOLTAGE REFRESH FOR SEMI-CIRCLE DRAIN...

NEGATIVE WORD LINE ENABLED PRE-BOOSTING STRATEGY TO IMPROVE NAND PR...

XOR DATA RECOVERY SCHEMES NONVOLATILE MEMORY DEVICES

HOLE CHANNEL PRE-CHARGE TO ENABLE LARGE-VOLUME IN-PLACE DATA SANITI...

GENERATION OF QUICK PASS WRITE BIASES IN A MEMORY DEVICE

LOOP DEPENDENT BIT LINE AND READ BIASES IN A MEMORY DEVICE

ACTIVE CURRENT CONSUMPTION SAVE MODE FOR NON-VOLATILE MEMORY USING...