Xiangdong Chen

Person

San Diego, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Semiconductor structure and method for forming the same
- Patent number 12,243,741
- Issue date Mar 4, 2025
- Taiwan Semiconductor Manufacturing Company Ltd.
- Johnny Chiahao Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low hold multi-bit flip-flop
- Patent number 12,040,800
- Issue date Jul 16, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Seid Hadi Rasouli
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integrated circuit structure and method for manufacturing the same
- Patent number 11,682,671
- Issue date Jun 20, 2023
- Taiwan Semiconductor Manufacturing Company Ltd.
- Wei-Ling Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of manufacturing the same
- Patent number 11,664,380
- Issue date May 30, 2023
- Taiwan Semiconductor Manufacturing Co., Ltd
- Guo-Huei Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low hold multi-bit flip-flop
- Patent number 11,558,040
- Issue date Jan 17, 2023
- Taiwan Semiconductor Manufacturing Campus, Ltd.
- Seid Hadi Rasouli
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Multi-bit standard cell
- Patent number 11,227,084
- Issue date Jan 18, 2022
- Taiwan Semiconductor Manufacturing Company Ltd.
- Jerry Chang Jui Kao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple via structure for high performance standard cells
- Patent number 11,133,803
- Issue date Sep 28, 2021
- QUALCOMM Incorporated
- Satyanarayana Sahu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of manufacturing the same
- Patent number 11,063,045
- Issue date Jul 13, 2021
- Taiwan Semiconductor Manufacturing Co., Ltd
- Guo-Huei Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Shunt power rail with short line effect
- Patent number 11,038,344
- Issue date Jun 15, 2021
- QUALCOMM Incorporated
- John Jianhong Zhu
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Metal oxide semiconductor device of an integrated circuit
- Patent number 10,965,289
- Issue date Mar 30, 2021
- QUALCOMM Incorporated
- Satyanarayana Sahu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Standard cell architecture for gate tie-off
- Patent number 10,784,345
- Issue date Sep 22, 2020
- QUALCOMM Incorporated
- Xiangdong Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Standard cell architecture for gate tie-off
- Patent number 10,777,640
- Issue date Sep 15, 2020
- QUALCOMM Incorporated
- Xiangdong Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High performance cell design in a technology with high density meta...
- Patent number 10,692,808
- Issue date Jun 23, 2020
- QUALCOMM Incorporated
- Renukprasad Hiremath
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Standard cell architecture for gate tie-off
- Patent number 10,600,866
- Issue date Mar 24, 2020
- QUALCOMM Incorporated
- Xiangdong Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Standard cell architecture with M1 layer unidirectional routing
- Patent number 10,593,700
- Issue date Mar 17, 2020
- QUALCOMM Incorporated
- Mukul Gupta
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Placement methodology to remove filler
- Patent number 10,490,543
- Issue date Nov 26, 2019
- QUALCOMM Incorporated
- Xiangdong Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuits (ICs) employing additional output vertical inte...
- Patent number 10,483,200
- Issue date Nov 19, 2019
- QUALCOMM Incorporated
- Haining Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit (IC) employing a channel structure layout having...
- Patent number 10,431,686
- Issue date Oct 1, 2019
- QUALCOMM Incorporated
- Haining Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multiple via structure for high performance standard cells
- Patent number 10,236,886
- Issue date Mar 19, 2019
- QUALCOMM Incorporated
- Satyanarayana Sahu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Semiconductor integrated circuits (ICs) employing localized low die...
- Patent number 10,199,462
- Issue date Feb 5, 2019
- QUALCOMM Incorporated
- Haining Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Hybrid coloring methodology for multi-pattern technology
- Patent number 10,175,571
- Issue date Jan 8, 2019
- QUALCOMM Incorporated
- Xiangdong Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Variable interconnect pitch for improved performance
- Patent number 9,984,029
- Issue date May 29, 2018
- QUALCOMM Incorporated
- Kern Rim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semi-data gated flop with low clock power/low internal power with m...
- Patent number 9,979,381
- Issue date May 22, 2018
- QUALCOMM Incorporated
- Seid Hadi Rasouli
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Standard cell architecture for parasitic resistance reduction
- Patent number 9,960,231
- Issue date May 1, 2018
- QUALCOMM Incorporated
- Xiangdong Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor devices with wider field gates for reduced gate resis...
- Patent number 9,941,377
- Issue date Apr 10, 2018
- QUALCOMM Incorporated
- Haining Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Standard cell architecture with M1 layer unidirectional routing
- Patent number 9,887,209
- Issue date Feb 6, 2018
- QUALCOMM Incorporated
- Mukul Gupta
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Metal oxide semiconductor cell device architecture with mixed diffu...
- Patent number 9,831,272
- Issue date Nov 28, 2017
- QUALCOMM Incorporated
- Xiangdong Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor integrated circuits (ICs) employing localized low die...
- Patent number 9,773,866
- Issue date Sep 26, 2017
- QUALCOMM Incorporated
- Haining Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low-area low clock-power flip-flop
- Patent number 9,755,618
- Issue date Sep 5, 2017
- QUALCOMM Incorporated
- Seid Hadi Rasouli
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
V1 and higher layers programmable ECO standard cells
- Patent number 9,640,522
- Issue date May 2, 2017
- QUALCOMM Incorporated
- Satyanarayana Sahu
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Low Hold Multi-Bit Flip-Flop
- Publication number 20240333265
- Publication date Oct 3, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Seid Hadi Rasouli
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
INTEGRATED CIRCUIT STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
- Publication number 20230275088
- Publication date Aug 31, 2023
- Taiwan Semiconductor Manufacturing company Ltd.
- WEI-LING CHANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME
- Publication number 20230260786
- Publication date Aug 17, 2023
- Taiwan Semiconductor Manufacturing company Ltd.
- JOHNNY CHIAHAO LI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
- Publication number 20230253406
- Publication date Aug 10, 2023
- TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY
- Guo-Huei WU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Low Hold Multi-Bit Flip-Flop
- Publication number 20230114367
- Publication date Apr 13, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Seid Hadi Rasouli
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
- Publication number 20210343715
- Publication date Nov 4, 2021
- TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY
- Guo-Huei WU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
- Publication number 20210143150
- Publication date May 13, 2021
- Taiwan Semiconductor Manufacturing company Ltd.
- WEI-LING CHANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Low Hold Multi-Bit Flip-Flop
- Publication number 20210099161
- Publication date Apr 1, 2021
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Hadi Rasouli
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
- Publication number 20200328212
- Publication date Oct 15, 2020
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Guo-Huei WU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTIPLE VIA STRUCTURE FOR HIGH PERFORMANCE STANDARD CELLS
- Publication number 20200266821
- Publication date Aug 20, 2020
- QUALCOMM Incorporated
- Satyanarayana SAHU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NOVEL STANDARD CELL ARCHITECTURE FOR GATE TIE-OFF
- Publication number 20200176562
- Publication date Jun 4, 2020
- QUALCOMM Incorporated
- Xiangdong Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STANDARD CELL ARCHITECTURE FOR GATE TIE-OFF
- Publication number 20200176563
- Publication date Jun 4, 2020
- QUALCOMM Incorporated
- Xiangdong Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-BIT STANDARD CELL
- Publication number 20200151297
- Publication date May 14, 2020
- Taiwan Semiconductor Manufacturing company Ltd.
- JERRY CHANG JUI KAO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SHUNT POWER RAIL WITH SHORT LINE EFFECT
- Publication number 20200044440
- Publication date Feb 6, 2020
- QUALCOMM Incorporated
- John Jianhong ZHU
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Application
STAGGERED SELF ALIGNED GATE CONTACT
- Publication number 20190252408
- Publication date Aug 15, 2019
- QUALCOMM Incorporated
- Hyeokjin LIM
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NOVEL STANDARD CELL ARCHITECTURE FOR GATE TIE-OFF
- Publication number 20190237542
- Publication date Aug 1, 2019
- QUALCOMM Incorporated
- Xiangdong Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PLACEMENT METHODOLOGY TO REMOVE FILLER
- Publication number 20190172823
- Publication date Jun 6, 2019
- QUALCOMM Incorporated
- Xiangdong Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLE VIA STRUCTURE FOR HIGH PERFORMANCE STANDARD CELLS
- Publication number 20190173473
- Publication date Jun 6, 2019
- QUALCOMM Incorporated
- Satyanarayana SAHU
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
HIGH PERFORMANCE CELL DESIGN IN A TECHNOLOGY WITH HIGH DENSITY META...
- Publication number 20190088591
- Publication date Mar 21, 2019
- QUALCOMM Incorporated
- Renukprasad Hiremath
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTIPLE VIA STRUCTURE FOR HIGH PERFORMANCE STANDARD CELLS
- Publication number 20180183439
- Publication date Jun 28, 2018
- QUALCOMM Incorporated
- Satyanarayana SAHU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CLOCK GATING CELL FOR LOW SETUP TIME FOR HIGH FREQUENCY DESIGNS
- Publication number 20180167058
- Publication date Jun 14, 2018
- QUALCOMM Incorporated
- Seid Hadi RASOULI
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
STANDARD CELL ARCHITECTURE WITH M1 LAYER UNIDIRECTIONAL ROUTING
- Publication number 20180122824
- Publication date May 3, 2018
- QUALCOMM Incorporated
- Mukul GUPTA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMI-DATA GATED FLOP WITH LOW CLOCK POWER/LOW INTERNAL POWER WITH M...
- Publication number 20180123568
- Publication date May 3, 2018
- QUALCOMM Incorporated
- Seid Hadi RASOULI
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
STANDARD CELL ARCHITECTURE FOR PARASITIC RESISTANCE REDUCTION
- Publication number 20170365657
- Publication date Dec 21, 2017
- QUALCOMM Incorporated
- Xiangdong CHEN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR INTEGRATED CIRCUITS (ICs) EMPLOYING LOCALIZED LOW DIE...
- Publication number 20170317167
- Publication date Nov 2, 2017
- QUALCOMM Incorporated
- Haining Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METAL OXIDE SEMICONDUCTOR CELL DEVICE ARCHITECTURE WITH MIXED DIFFU...
- Publication number 20170287933
- Publication date Oct 5, 2017
- QUALCOMM Incorporated
- Xiangdong CHEN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOW-AREA LOW CLOCK-POWER FLIP-FLOP
- Publication number 20170257080
- Publication date Sep 7, 2017
- QUALCOMM Incorporated
- Seid Hadi RASOULI
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SEMICONDUCTOR DEVICES WITH WIDER FIELD GATES FOR REDUCED GATE RESIS...
- Publication number 20170186848
- Publication date Jun 29, 2017
- QUALCOMM Incorporated
- Haining Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR INTEGRATED CIRCUITS (ICs) EMPLOYING LOCALIZED LOW DIE...
- Publication number 20160372544
- Publication date Dec 22, 2016
- QUALCOMM Incorporated
- Haining Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HYBRID COLORING METHODOLOGY FOR MULTI-PATTERN TECHNOLOGY
- Publication number 20160370699
- Publication date Dec 22, 2016
- QUALCOMM Incorporated
- Xiangdong CHEN
- G06 - COMPUTING CALCULATING COUNTING

Xiangdong Chen

Person

Patents Grantslast 30 patents

Semiconductor structure and method for forming the same

Low hold multi-bit flip-flop

Integrated circuit structure and method for manufacturing the same

Semiconductor device and method of manufacturing the same

Low hold multi-bit flip-flop

Multi-bit standard cell

Multiple via structure for high performance standard cells

Semiconductor device and method of manufacturing the same

Shunt power rail with short line effect

Metal oxide semiconductor device of an integrated circuit

Standard cell architecture for gate tie-off

Standard cell architecture for gate tie-off

High performance cell design in a technology with high density meta...

Standard cell architecture for gate tie-off

Standard cell architecture with M1 layer unidirectional routing

Placement methodology to remove filler

Integrated circuits (ICs) employing additional output vertical inte...

Integrated circuit (IC) employing a channel structure layout having...

Multiple via structure for high performance standard cells

Semiconductor integrated circuits (ICs) employing localized low die...

Hybrid coloring methodology for multi-pattern technology

Variable interconnect pitch for improved performance

Semi-data gated flop with low clock power/low internal power with m...

Standard cell architecture for parasitic resistance reduction

Semiconductor devices with wider field gates for reduced gate resis...

Standard cell architecture with M1 layer unidirectional routing

Metal oxide semiconductor cell device architecture with mixed diffu...

Semiconductor integrated circuits (ICs) employing localized low die...

Low-area low clock-power flip-flop

V1 and higher layers programmable ECO standard cells

Patents Applicationslast 30 patents

Low Hold Multi-Bit Flip-Flop

INTEGRATED CIRCUIT STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Low Hold Multi-Bit Flip-Flop

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

INTEGRATED CIRCUIT STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

Low Hold Multi-Bit Flip-Flop

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

MULTIPLE VIA STRUCTURE FOR HIGH PERFORMANCE STANDARD CELLS

NOVEL STANDARD CELL ARCHITECTURE FOR GATE TIE-OFF

STANDARD CELL ARCHITECTURE FOR GATE TIE-OFF

MULTI-BIT STANDARD CELL

SHUNT POWER RAIL WITH SHORT LINE EFFECT

STAGGERED SELF ALIGNED GATE CONTACT

NOVEL STANDARD CELL ARCHITECTURE FOR GATE TIE-OFF

PLACEMENT METHODOLOGY TO REMOVE FILLER

MULTIPLE VIA STRUCTURE FOR HIGH PERFORMANCE STANDARD CELLS

HIGH PERFORMANCE CELL DESIGN IN A TECHNOLOGY WITH HIGH DENSITY META...

MULTIPLE VIA STRUCTURE FOR HIGH PERFORMANCE STANDARD CELLS

CLOCK GATING CELL FOR LOW SETUP TIME FOR HIGH FREQUENCY DESIGNS

STANDARD CELL ARCHITECTURE WITH M1 LAYER UNIDIRECTIONAL ROUTING

SEMI-DATA GATED FLOP WITH LOW CLOCK POWER/LOW INTERNAL POWER WITH M...

STANDARD CELL ARCHITECTURE FOR PARASITIC RESISTANCE REDUCTION

SEMICONDUCTOR INTEGRATED CIRCUITS (ICs) EMPLOYING LOCALIZED LOW DIE...

METAL OXIDE SEMICONDUCTOR CELL DEVICE ARCHITECTURE WITH MIXED DIFFU...

LOW-AREA LOW CLOCK-POWER FLIP-FLOP

SEMICONDUCTOR DEVICES WITH WIDER FIELD GATES FOR REDUCED GATE RESIS...

SEMICONDUCTOR INTEGRATED CIRCUITS (ICs) EMPLOYING LOCALIZED LOW DIE...

HYBRID COLORING METHODOLOGY FOR MULTI-PATTERN TECHNOLOGY