Xiao-Chun Mu

Person

Saratoga, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Reliable adhesion layer interface structure for polymer memory elec...
- Patent number 7,078,240
- Issue date Jul 18, 2006
- Intel Corporation
- Jian Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stepped structure for a multi-rank, stacked polymer memory device a...
- Patent number 7,018,853
- Issue date Mar 28, 2006
- Intel Corporation
- Jian Li
- G11 - INFORMATION STORAGE
Information Patent Grant
Method to protect an encapsulated die package during back grinding...
- Patent number 6,964,889
- Issue date Nov 15, 2005
- Intel Corporation
- Qing Ma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked ferroelectric memory device and method of making same
- Patent number 6,960,479
- Issue date Nov 1, 2005
- Intel Corporation
- Jian Li
- G11 - INFORMATION STORAGE
Information Patent Grant
Low-voltage and interface damage-free polymer memory device
- Patent number 6,952,017
- Issue date Oct 4, 2005
- Intel Corporation
- Jian Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to protect an encapsulated die package during back grinding...
- Patent number 6,902,950
- Issue date Jun 7, 2005
- Intel Corporation
- Qing Ma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Discrete polymer memory array and method of making same
- Patent number 6,858,862
- Issue date Feb 22, 2005
- Intel Corporation
- Jian Li
- G11 - INFORMATION STORAGE
Information Patent Grant
Reliable adhesion layer interface structure for polymer memory elec...
- Patent number 6,798,003
- Issue date Sep 28, 2004
- Intel Corporation
- Jian Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low-voltage and interface damage-free polymer memory device
- Patent number 6,756,620
- Issue date Jun 29, 2004
- Intel Corporation
- Jian Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stepped structure for a multi-rank, stacked polymer memory device a...
- Patent number 6,624,457
- Issue date Sep 23, 2003
- Intel Corporation
- Jian Li
- G11 - INFORMATION STORAGE
Information Patent Grant
Active interposer technology for high performance CMOS packaging ap...
- Patent number 6,600,364
- Issue date Jul 29, 2003
- Intel Corporation
- Chunlin Liang
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated core microelectronic package
- Patent number 6,586,822
- Issue date Jul 1, 2003
- Intel Corporation
- Quat T. Vu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for forming microelectronic packages and intermediate struc...
- Patent number 6,586,836
- Issue date Jul 1, 2003
- Intel Corporation
- Qing Ma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Embedded recess in polymer memory package and method of making same
- Patent number 6,524,887
- Issue date Feb 25, 2003
- Intel Corporation
- Jian Li
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and an apparatus for forming an under bump metallization str...
- Patent number 6,461,954
- Issue date Oct 8, 2002
- Intel Corporation
- Jian Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for making active interposer for high performance packaging...
- Patent number 6,461,895
- Issue date Oct 8, 2002
- Intel Corporation
- Chunlin Liang
- G11 - INFORMATION STORAGE
Information Patent Grant
Method to protect an encapsulated die package during back grinding...
- Patent number 6,423,570
- Issue date Jul 23, 2002
- Intel Corporation
- Qing Ma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Flip-chip on flex for high performance packaging applications
- Patent number 6,365,962
- Issue date Apr 2, 2002
- Intel Corporation
- Chunlin Liang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and an apparatus for forming an under bump metallization str...
- Patent number 6,312,830
- Issue date Nov 6, 2001
- Intel Corporation
- Jian Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High density plasma physical vapor deposition
- Patent number 5,792,522
- Issue date Aug 11, 1998
- Intel Corporation
- Shu Jin
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Methods of forming an interconnect on a semiconductor substrate
- Patent number 5,612,254
- Issue date Mar 18, 1997
- Intel Corporation
- Xiao-Chun Mu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for the anisotropic etching of metal films in the fabricatio...
- Patent number 5,350,484
- Issue date Sep 27, 1994
- Intel Corporation
- Donald S. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Intelligent security device
- Patent number 5,343,524
- Issue date Aug 30, 1994
- Xiao-Chun Mu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Etchback process for tungsten contact/via filling
- Patent number 5,167,760
- Issue date Dec 1, 1992
- Intel Corporation
- Xiao-Chun Mu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Novel etch back process for tungsten contact/via filling
- Patent number 5,035,768
- Issue date Jul 30, 1991
- Intel Corporation
- Xiao-Chun Mu
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Plasma etching process for refractory metal vias
- Patent number 4,980,018
- Issue date Dec 25, 1990
- Intel Corporation
- Xiao-Chun Mu
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Low-voltage and interface damage-free polymer memory device
- Publication number 20040150023
- Publication date Aug 5, 2004
- Jian Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Reliable adhesion layer interface structure for polymer memory elec...
- Publication number 20040152231
- Publication date Aug 5, 2004
- Jian Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated core microelectronic package
- Publication number 20040094830
- Publication date May 20, 2004
- Intel Corporation
- Quat T. Vu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Stepped structure for a multi-rank, stacked polymer memory device a...
- Publication number 20030015740
- Publication date Jan 23, 2003
- Intel Corporation
- Jian Li
- B82 - NANO-TECHNOLOGY
Information Patent Application
Reliable adhesion layer interface structure for polymer memory elec...
- Publication number 20030017623
- Publication date Jan 23, 2003
- Intel Corporation
- Jian Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Stacked ferroelectric memory device and method of making same
- Publication number 20030017627
- Publication date Jan 23, 2003
- Intel Corporation
- Jian Li
- B82 - NANO-TECHNOLOGY
Information Patent Application
EMBEDDED RECESS IN POLYMER MEMORY PACKAGE AND METHOD OF MAKING SAME
- Publication number 20030017643
- Publication date Jan 23, 2003
- Intel Corporation
- Jian Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Discrete polymer memory array and method of making same
- Publication number 20030001151
- Publication date Jan 2, 2003
- Intel Corporation
- Jian Li
- B82 - NANO-TECHNOLOGY
Information Patent Application
Low-voltage and interface damage-free polymer memory device
- Publication number 20030001176
- Publication date Jan 2, 2003
- Intel Corporation
- Jian Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method to protect an encapsulated die package during back grinding...
- Publication number 20020127780
- Publication date Sep 12, 2002
- Qing Ma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method to protect an encapsulated die package during back grinding...
- Publication number 20020127769
- Publication date Sep 12, 2002
- Qing Ma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Flip-chip on flex for high performance packaging applications
- Publication number 20020081774
- Publication date Jun 27, 2002
- Chunlin Liang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Microelectronic package having an integrated heat sink and build-up...
- Publication number 20020070443
- Publication date Jun 13, 2002
- Xiao-Chun Mu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method and an apparatus for forming an under bump metallization str...
- Publication number 20020028338
- Publication date Mar 7, 2002
- Jian Li
- H01 - BASIC ELECTRIC ELEMENTS

Xiao-Chun Mu

Person

Patents Grantslast 30 patents

Reliable adhesion layer interface structure for polymer memory elec...

Stepped structure for a multi-rank, stacked polymer memory device a...

Method to protect an encapsulated die package during back grinding...

Stacked ferroelectric memory device and method of making same

Low-voltage and interface damage-free polymer memory device

Method to protect an encapsulated die package during back grinding...

Discrete polymer memory array and method of making same

Reliable adhesion layer interface structure for polymer memory elec...

Low-voltage and interface damage-free polymer memory device

Stepped structure for a multi-rank, stacked polymer memory device a...

Active interposer technology for high performance CMOS packaging ap...

Integrated core microelectronic package

Process for forming microelectronic packages and intermediate struc...

Embedded recess in polymer memory package and method of making same

Method and an apparatus for forming an under bump metallization str...

Process for making active interposer for high performance packaging...

Method to protect an encapsulated die package during back grinding...

Flip-chip on flex for high performance packaging applications

Method and an apparatus for forming an under bump metallization str...

High density plasma physical vapor deposition

Methods of forming an interconnect on a semiconductor substrate

Method for the anisotropic etching of metal films in the fabricatio...

Intelligent security device

Etchback process for tungsten contact/via filling

Novel etch back process for tungsten contact/via filling

Plasma etching process for refractory metal vias

Patents Applicationslast 30 patents

Low-voltage and interface damage-free polymer memory device

Reliable adhesion layer interface structure for polymer memory elec...

Integrated core microelectronic package

Stepped structure for a multi-rank, stacked polymer memory device a...

Reliable adhesion layer interface structure for polymer memory elec...

Stacked ferroelectric memory device and method of making same

EMBEDDED RECESS IN POLYMER MEMORY PACKAGE AND METHOD OF MAKING SAME

Discrete polymer memory array and method of making same

Low-voltage and interface damage-free polymer memory device

Method to protect an encapsulated die package during back grinding...

Method to protect an encapsulated die package during back grinding...

Flip-chip on flex for high performance packaging applications

Microelectronic package having an integrated heat sink and build-up...

Method and an apparatus for forming an under bump metallization str...