Xiaodong Yang

Person

Hopewell Junction, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Integrated circuits and methods for fabricating integrated circuits...
- Patent number 9,419,126
- Issue date Aug 16, 2016
- GLOBALFOUNDRIES, INC.
- Xiaodong Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Containment structure for epitaxial growth in non-planar semiconduc...
- Patent number 9,142,640
- Issue date Sep 22, 2015
- GLOBALFOUNDRIES Inc.
- Xusheng Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Shallow trench isolation
- Patent number 9,136,330
- Issue date Sep 15, 2015
- GLOBALFOUNDRIES, INC.
- Yanxiang Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-adjusting latch-up resistance for CMOS devices
- Patent number 8,841,732
- Issue date Sep 23, 2014
- GLOBALFOUNDRIES, INC.
- Yanxiang Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of manufacturing semiconductor devices including replacement...
- Patent number 8,835,292
- Issue date Sep 16, 2014
- International Business Machines Corporation
- Michael P. Chudzik
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming bulk FinFET devices with replacement gates so as...
- Patent number 8,809,178
- Issue date Aug 19, 2014
- GLOBALFOUNDRIES Inc.
- Yanxiang Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Transistor with reduced parasitic capacitance
- Patent number 8,809,962
- Issue date Aug 19, 2014
- GLOBALFOUNDRIES Inc.
- Yanxiang Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming N-shaped bottom stress liner
- Patent number 8,669,616
- Issue date Mar 11, 2014
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Xiaodong Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for fabricating a FINFET integrated circuit on a bulk silic...
- Patent number 8,637,372
- Issue date Jan 28, 2014
- GLOBALFOUNDRIES, INC.
- Yanxiang Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming N-shaped bottom stress liner
- Patent number 8,557,668
- Issue date Oct 15, 2013
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Xiaodong Yang
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
SHALLOW TRENCH ISOLATION
- Publication number 20150348830
- Publication date Dec 3, 2015
- GLOBALFOUNDRIES INC.
- Yanxiang Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SHALLOW TRENCH ISOLATION
- Publication number 20150021702
- Publication date Jan 22, 2015
- GLOBALFOUNDRIES INC.
- Yanxiang Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUITS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS...
- Publication number 20140264613
- Publication date Sep 18, 2014
- GLOBALFOUNDRIES, Inc.
- Xiaodong Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD AND STRUCTURE FOR TRANSISTOR WITH REDUCED DRAIN-INDUCED BARR...
- Publication number 20140159052
- Publication date Jun 12, 2014
- GLOBALFOUNDRIES INC.
- Jinping Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES INCLUDING REPLACEMENT...
- Publication number 20140120708
- Publication date May 1, 2014
- GLOBALFOUNDRIES INC.
- Michael P. Chudzik
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FORMING N-SHAPED BOTTOM STRESS LINER
- Publication number 20140015020
- Publication date Jan 16, 2014
- Xiaodong YANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FORMING BULK FINFET DEVICES WITH REPLACEMENT GATES SO AS...
- Publication number 20130224945
- Publication date Aug 29, 2013
- GLOBALFOUNDRIES INC.
- Yanxiang Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FORMING N-SHAPED BOTTOM STRESS LINER
- Publication number 20130181260
- Publication date Jul 18, 2013
- GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Xiaodong Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TRANSISTOR WITH REDUCED PARASITIC CAPACITANCE
- Publication number 20130049142
- Publication date Feb 28, 2013
- International Business Machines Corporation
- Yanxiang Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ADJUSTING LATCH-UP RESISTANCE FOR CMOS DEVICES
- Publication number 20130032890
- Publication date Feb 7, 2013
- Yanxiang Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS FOR FABRICATING A FINFET INTEGRATED CIRCUIT ON A BULK SILIC...
- Publication number 20130005103
- Publication date Jan 3, 2013
- GLOBALFOUNDRIES INC.
- Yanxiang Liu
- H01 - BASIC ELECTRIC ELEMENTS

Xiaodong Yang

Person

Patents Grantslast 30 patents

Integrated circuits and methods for fabricating integrated circuits...

Containment structure for epitaxial growth in non-planar semiconduc...

Shallow trench isolation

Self-adjusting latch-up resistance for CMOS devices

Method of manufacturing semiconductor devices including replacement...

Methods of forming bulk FinFET devices with replacement gates so as...

Transistor with reduced parasitic capacitance

Method for forming N-shaped bottom stress liner

Methods for fabricating a FINFET integrated circuit on a bulk silic...

Method for forming N-shaped bottom stress liner

Patents Applicationslast 30 patents

SHALLOW TRENCH ISOLATION

SHALLOW TRENCH ISOLATION

INTEGRATED CIRCUITS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS...

METHOD AND STRUCTURE FOR TRANSISTOR WITH REDUCED DRAIN-INDUCED BARR...

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES INCLUDING REPLACEMENT...

METHOD FOR FORMING N-SHAPED BOTTOM STRESS LINER

METHODS OF FORMING BULK FINFET DEVICES WITH REPLACEMENT GATES SO AS...

METHOD FOR FORMING N-SHAPED BOTTOM STRESS LINER

TRANSISTOR WITH REDUCED PARASITIC CAPACITANCE

SELF-ADJUSTING LATCH-UP RESISTANCE FOR CMOS DEVICES

METHODS FOR FABRICATING A FINFET INTEGRATED CIRCUIT ON A BULK SILIC...