Xiaojian Yang

Person

Sunnyvale, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Sub-FPGA level compilation platform with adjustable dynamic region...
- Patent number 11,681,846
- Issue date Jun 20, 2023
- Xilinx, Inc.
- Xiaojian Yang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable integrated circuits for emulation
- Patent number 10,956,638
- Issue date Mar 23, 2021
- Xilinx, Inc.
- Bart Reynolds
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Evaluation of nets for suitability of time domain multiplexing duri...
- Patent number 10,878,154
- Issue date Dec 29, 2020
- Xilinx, Inc.
- Raoul Badaoui
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock tree routing in programmable logic device
- Patent number 10,860,765
- Issue date Dec 8, 2020
- Xilinx, Inc.
- Wuxi Li
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Timing-closure methodology involving clock network in hardware designs
- Patent number 10,528,697
- Issue date Jan 7, 2020
- Xilinx, Inc.
- Wei Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable integrated circuits for emulation
- Patent number 10,402,521
- Issue date Sep 3, 2019
- Xilinx, Inc.
- Bart Reynolds
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit design implementation using control-set based merging and m...
- Patent number 10,242,150
- Issue date Mar 26, 2019
- Xilinx, Inc.
- Sabyasachi Das
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processing of a circuit design for debugging
- Patent number 10,126,361
- Issue date Nov 13, 2018
- Xilinx, Inc.
- Xiaojian Yang
- G01 - MEASURING TESTING
Information Patent Grant
Partitioning circuit designs for implementation within multi-die in...
- Patent number 10,108,773
- Issue date Oct 23, 2018
- Xilinx, Inc.
- Grigor S. Gasparyan
- G06 - COMPUTING CALCULATING COUNTING

Xiaojian Yang

Person

Patents Grantslast 30 patents

Sub-FPGA level compilation platform with adjustable dynamic region...

Programmable integrated circuits for emulation

Evaluation of nets for suitability of time domain multiplexing duri...

Clock tree routing in programmable logic device

Timing-closure methodology involving clock network in hardware designs

Programmable integrated circuits for emulation

Circuit design implementation using control-set based merging and m...

Processing of a circuit design for debugging

Partitioning circuit designs for implementation within multi-die in...