Xiaoning Ye

Person

Portland, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Magnetically secured semiconductor chip package loading assembly
- Patent number 12,309,933
- Issue date May 20, 2025
- Intel Corporation
- Phil Geng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual-stripline with crosstalk cancellation
- Patent number 12,113,265
- Issue date Oct 8, 2024
- Intel Corporation
- Albert Sutono
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Technologies for verifying a de-embedder for interconnect measurement
- Patent number 11,169,194
- Issue date Nov 9, 2021
- Intel Corporation
- Xiaoning Ye
- G01 - MEASURING TESTING
Information Patent Grant
Connector with active circuit
- Patent number 10,965,047
- Issue date Mar 30, 2021
- Intel Corporation
- Jong-Ru Guo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dielectric coating for crosstalk reduction
- Patent number 10,925,152
- Issue date Feb 16, 2021
- Intel Corporation
- Albert Sutono
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Reduction of insertion loss in printed circuit board signal traces
- Patent number 10,827,627
- Issue date Nov 3, 2020
- Intel Corporation
- Xiaoning Ye
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Technologies for verifying a de-embedder for interconnect measurement
- Patent number 10,571,501
- Issue date Feb 25, 2020
- Intel Corporation
- Xiaoning Ye
- G01 - MEASURING TESTING
Information Patent Grant
Signal routing with reduced crosstalk
- Patent number 9,893,761
- Issue date Feb 13, 2018
- Intel Corporation
- Xiaoning Ye
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Absorbing termination in an interconnect
- Patent number 9,750,129
- Issue date Aug 29, 2017
- Intel Corporation
- Shaowu Huang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Devices and methods to reduce differential signal pair crosstalk
- Patent number 9,554,454
- Issue date Jan 24, 2017
- Intel Corporation
- Chong Richard Zhao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Absorbing termination in an interconnect
- Patent number 9,485,854
- Issue date Nov 1, 2016
- Intel Corporation
- Shaowu Huang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Crosstalk cancellation and/or reduction
- Patent number 9,293,798
- Issue date Mar 22, 2016
- Intel Corporation
- Xiaoning Ye
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Apparatus for differential far-end crosstalk reduction
- Patent number 9,113,555
- Issue date Aug 18, 2015
- Intel Corporation
- Raul Enriquez Shibayama
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Differential signal crosstalk reduction
- Patent number 8,624,687
- Issue date Jan 7, 2014
- Intel Corporation
- Xiaoning Ye
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Determining a bit error rate (BER) using interpolation and superpos...
- Patent number 7,965,763
- Issue date Jun 21, 2011
- Intel Corporation
- Kai Xiao
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Reducing crosstalk in electronic devices having microstrip lines co...
- Patent number 7,573,359
- Issue date Aug 11, 2009
- Intel Corporation
- Richard K. Kunze
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Skew compensation by changing ground parasitic for traces
- Patent number 7,450,396
- Issue date Nov 11, 2008
- Intel Corporation
- Chunfei Ye
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
System to control signal line capacitance
- Patent number 7,361,994
- Issue date Apr 22, 2008
- Intel Corporation
- Xiaoning Ye
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Methods for minimizing the impedance discontinuity between a conduc...
- Patent number 7,034,544
- Issue date Apr 25, 2006
- Intel Corporation
- Xiaoning Ye
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
COMPOSITE BACKPLATE ARCHITECTURES FOR BACKSIDE POWER DELIVERY AND A...
- Publication number 20250089192
- Publication date Mar 13, 2025
- Intel Corporation
- Phil Geng
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
TRANSVERSE MAGNETIC MODE SPLIT POST DIELECTRIC RESONATOR
- Publication number 20250070443
- Publication date Feb 27, 2025
- THE CURATORS OF THE UNIVERSITY OF MISSOURI
- DongHyun Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DUAL IN-LINE MEMORY MODULE (DIMM) SOLUTION THAT INCLUDES FLEXIBLE T...
- Publication number 20240237193
- Publication date Jul 11, 2024
- Intel Corporation
- Yi HUANG
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
PRINTED CIRCUIT BOARD PIN FIELD SIGNAL ROUTING
- Publication number 20240176941
- Publication date May 30, 2024
- Intel Corporation
- Xiaoning Ye
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-ENTRY SOCKET POWER DELIVERY STRUCTURE AND BACKPLATE
- Publication number 20240179832
- Publication date May 30, 2024
- Phil Geng
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
INTEGRATED CIRCUIT SUPPORTS WITH MICROSTRIPS
- Publication number 20240088069
- Publication date Mar 14, 2024
- Intel Corporation
- Wenzhi Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT SUPPORTS WITH MICROSTRIPS
- Publication number 20240063134
- Publication date Feb 22, 2024
- Intel Corporation
- Xiaoning Ye
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DUAL-STRIPLINE WITH CROSSTALK CANCELLATION
- Publication number 20220311114
- Publication date Sep 29, 2022
- Intel Corporation
- Albert Sutono
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT SUPPORTS WITH MICROSTRIPS
- Publication number 20220270989
- Publication date Aug 25, 2022
- Intel Corporation
- Albert Sutono
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MAGNETICALLY SECURED SEMICONDUCTOR CHIP PACKAGE LOADING ASSEMBLY
- Publication number 20210378099
- Publication date Dec 2, 2021
- Intel Corporation
- Phil GENG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SKEW DETECTION AND COMPENSATION FOR HIGH SPEED I/O LINKS
- Publication number 20210311120
- Publication date Oct 7, 2021
- Intel Corporation
- Jong-Ru Guo
- G01 - MEASURING TESTING
Information Patent Application
TECHNOLOGIES FOR VERIFYING A DE-EMBEDDER FOR INTERCONNECT MEASUREMENT
- Publication number 20200292603
- Publication date Sep 17, 2020
- Intel Corporation
- Xiaoning Ye
- G01 - MEASURING TESTING
Information Patent Application
CONNECTOR WITH ACTIVE CIRCUIT
- Publication number 20190288421
- Publication date Sep 19, 2019
- Intel Corporation
- Jong-Ru Guo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
REDUCTION OF INSERTION LOSS IN PRINTED CIRCUIT BOARD SIGNAL TRACES
- Publication number 20190223299
- Publication date Jul 18, 2019
- Intel Corporation
- Xiaoning Ye
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
DIELECTRIC COATING FOR CROSSTALK REDUCTION
- Publication number 20190045623
- Publication date Feb 7, 2019
- Intel Corporation
- Albert Sutono
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TECHNOLOGIES FOR VERIFYING A DE-EMBEDDER FOR INTERCONNECT MEASUREMENT
- Publication number 20170269136
- Publication date Sep 21, 2017
- Intel Corporation
- Xiaoning Ye
- G01 - MEASURING TESTING
Information Patent Application
ABSORBING TERMINATION IN AN INTERCONNECT
- Publication number 20170006698
- Publication date Jan 5, 2017
- Intel Corporation
- Shaowu Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEVICES AND METHODS TO REDUCE DIFFERENTIAL SIGNAL PAIR CROSSTALK
- Publication number 20160181682
- Publication date Jun 23, 2016
- Chong Richard Zhao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SIGNAL ROUTING WITH REDUCED CROSSTALK
- Publication number 20160094272
- Publication date Mar 31, 2016
- Intel Corporation
- XIAONING YE
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
ABSORBING TERMINATION IN AN INTERCONNECT
- Publication number 20160057851
- Publication date Feb 25, 2016
- Intel Corporation
- Shaowu Huang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus for Differential Far-End Crosstalk Reduction
- Publication number 20140179162
- Publication date Jun 26, 2014
- Raul Enriquez Shibayama
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
DIFFERENTIAL SIGNAL CROSSTALK REDUCTION
- Publication number 20140091873
- Publication date Apr 3, 2014
- Xiaoning Ye
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CROSSTALK CANCELLATION AND/OR REDUCTION
- Publication number 20130278348
- Publication date Oct 24, 2013
- Xiaoning Ye
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DIFFERENTIAL SIGNAL CROSSTALK REDUCTION
- Publication number 20120161893
- Publication date Jun 28, 2012
- Xiaoning Ye
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CROSSTALK REDUCTION ON MICROSTRIP ROUTING
- Publication number 20120160542
- Publication date Jun 28, 2012
- Olufemi B. Oluwafemi
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Determining a bit error rate (BER) using interpolation and superpos...
- Publication number 20090110042
- Publication date Apr 30, 2009
- Kai Xiao
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Skew Compensation by Changing Ground Parasitic For Traces
- Publication number 20080314620
- Publication date Dec 25, 2008
- Chunfei Ye
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Reducing crosstalk in electronic devices having microstrip lines
- Publication number 20080238584
- Publication date Oct 2, 2008
- Richard K. Kunze
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Skew compensation by changing ground parasitic for traces
- Publication number 20080080155
- Publication date Apr 3, 2008
- Chunfei Ye
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Reducing signal crosstalk of edge-card connector
- Publication number 20070149060
- Publication date Jun 28, 2007
- Xiaoning Ye
- H01 - BASIC ELECTRIC ELEMENTS

Xiaoning Ye

Person

Patents Grantslast 30 patents

Magnetically secured semiconductor chip package loading assembly

Dual-stripline with crosstalk cancellation

Technologies for verifying a de-embedder for interconnect measurement

Connector with active circuit

Dielectric coating for crosstalk reduction

Reduction of insertion loss in printed circuit board signal traces

Technologies for verifying a de-embedder for interconnect measurement

Signal routing with reduced crosstalk

Absorbing termination in an interconnect

Devices and methods to reduce differential signal pair crosstalk

Absorbing termination in an interconnect

Crosstalk cancellation and/or reduction

Apparatus for differential far-end crosstalk reduction

Differential signal crosstalk reduction

Determining a bit error rate (BER) using interpolation and superpos...

Reducing crosstalk in electronic devices having microstrip lines co...

Skew compensation by changing ground parasitic for traces

System to control signal line capacitance

Methods for minimizing the impedance discontinuity between a conduc...

Patents Applicationslast 30 patents

COMPOSITE BACKPLATE ARCHITECTURES FOR BACKSIDE POWER DELIVERY AND A...

TRANSVERSE MAGNETIC MODE SPLIT POST DIELECTRIC RESONATOR

DUAL IN-LINE MEMORY MODULE (DIMM) SOLUTION THAT INCLUDES FLEXIBLE T...

PRINTED CIRCUIT BOARD PIN FIELD SIGNAL ROUTING

MULTI-ENTRY SOCKET POWER DELIVERY STRUCTURE AND BACKPLATE

INTEGRATED CIRCUIT SUPPORTS WITH MICROSTRIPS

INTEGRATED CIRCUIT SUPPORTS WITH MICROSTRIPS

DUAL-STRIPLINE WITH CROSSTALK CANCELLATION

INTEGRATED CIRCUIT SUPPORTS WITH MICROSTRIPS

MAGNETICALLY SECURED SEMICONDUCTOR CHIP PACKAGE LOADING ASSEMBLY

SKEW DETECTION AND COMPENSATION FOR HIGH SPEED I/O LINKS

TECHNOLOGIES FOR VERIFYING A DE-EMBEDDER FOR INTERCONNECT MEASUREMENT

CONNECTOR WITH ACTIVE CIRCUIT

REDUCTION OF INSERTION LOSS IN PRINTED CIRCUIT BOARD SIGNAL TRACES

DIELECTRIC COATING FOR CROSSTALK REDUCTION

TECHNOLOGIES FOR VERIFYING A DE-EMBEDDER FOR INTERCONNECT MEASUREMENT

ABSORBING TERMINATION IN AN INTERCONNECT

DEVICES AND METHODS TO REDUCE DIFFERENTIAL SIGNAL PAIR CROSSTALK

SIGNAL ROUTING WITH REDUCED CROSSTALK

ABSORBING TERMINATION IN AN INTERCONNECT

Apparatus for Differential Far-End Crosstalk Reduction

DIFFERENTIAL SIGNAL CROSSTALK REDUCTION

CROSSTALK CANCELLATION AND/OR REDUCTION

DIFFERENTIAL SIGNAL CROSSTALK REDUCTION

CROSSTALK REDUCTION ON MICROSTRIP ROUTING

Determining a bit error rate (BER) using interpolation and superpos...

Skew Compensation by Changing Ground Parasitic For Traces

Reducing crosstalk in electronic devices having microstrip lines

Skew compensation by changing ground parasitic for traces

Reducing signal crosstalk of edge-card connector