Xiaoping Tang

Person

Mohegan Lake, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Layout decomposition method and apparatus for multiple patterning l...
- Patent number 8,799,844
- Issue date Aug 5, 2014
- International Business Machines Corporation
- Minsik Cho
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Relative ordering circuit synthesis
- Patent number 8,756,541
- Issue date Jun 17, 2014
- International Business Machines Corporation
- Minsik Cho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for fixing pin mismatch in layout migration
- Patent number 8,627,247
- Issue date Jan 7, 2014
- International Business Machines Corporation
- Kevin W. McCullen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Parallel solving of layout optimization
- Patent number 8,555,229
- Issue date Oct 8, 2013
- International Business Machines Corporation
- Xiaoping Tang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Decomposing layout for triple patterning lithography
- Patent number 8,484,607
- Issue date Jul 9, 2013
- International Business Machines Corporation
- Xiaoping Tang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Structural migration of integrated circuit layout
- Patent number 8,423,941
- Issue date Apr 16, 2013
- International Business Machines Corporation
- Fook-Luen Heng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods to obtain a feasible integer solution in a hierarchical cir...
- Patent number 8,302,062
- Issue date Oct 30, 2012
- International Business Machines Corporation
- Michael S. Gray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Handling two-dimensional constraints in integrated circuit layout
- Patent number 8,296,706
- Issue date Oct 23, 2012
- International Business Machines Corporation
- Michael S. Gray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
VLSI artwork legalization for hierarchical designs with multiple gr...
- Patent number 7,962,879
- Issue date Jun 14, 2011
- International Business Machines Corporation
- Xiaoping Tang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system to redistribute white space for minimizing wire l...
- Patent number 7,904,840
- Issue date Mar 8, 2011
- International Business Machines Corporation
- Xiaoping Tang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adaptive weighting method for layout optimization with multiple pri...
- Patent number 7,895,562
- Issue date Feb 22, 2011
- International Business Machines Corporation
- Michael S. Gray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Obtaining a feasible integer solution in a hierarchical circuit lay...
- Patent number 7,761,818
- Issue date Jul 20, 2010
- International Business Machines Corporation
- Michael S. Gray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
VLSI artwork legalization for hierarchical designs with multiple gr...
- Patent number 7,437,691
- Issue date Oct 14, 2008
- International Business Machines Corporation
- Xiaoping Tang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system to redistribute white space for minimizing wire l...
- Patent number 7,305,641
- Issue date Dec 4, 2007
- International Business Machines Corporation
- Xiaoping Tang
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
SYSTEMS AND METHODS FOR FIXING PIN MISMATCH IN LAYOUT MIGRATION
- Publication number 20140019931
- Publication date Jan 16, 2014
- International Business Machines Corporation
- Kevin W. MCCULLEN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RELATIVE ORDERING CIRCUIT SYNTHESIS
- Publication number 20130263068
- Publication date Oct 3, 2013
- International Business Machines Corporation
- Minsik Cho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STRUCTURAL MIGRATION OF INTEGRATED CIRCUIT LAYOUT
- Publication number 20130042217
- Publication date Feb 14, 2013
- International Business Machines Corporation
- Fook-Luen HENG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PARALLEL SOLVING OF LAYOUT OPTIMIZATION
- Publication number 20120311517
- Publication date Dec 6, 2012
- International Business Machines Corporation
- Xiaoping Tang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LAYOUT DECOMPOSITION METHOD AND APPARATUS FOR MULTIPLE PATTERNING L...
- Publication number 20120196230
- Publication date Aug 2, 2012
- International Business Machines Corporation
- Minsik Cho
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
HANDLING TWO-DIMENSIONAL CONSTRAINTS IN INTEGRATED CIRCUIT LAYOUT
- Publication number 20110265055
- Publication date Oct 27, 2011
- International Business Machines Corporation
- Michael S. Gray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS TO OBTAIN A FEASIBLE INTEGER SOLUTION IN A HIERARCHICAL CIR...
- Publication number 20100153892
- Publication date Jun 17, 2010
- International Business Machines Corporation
- Michael S. Gray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADAPTIVE WEIGHTING METHOD FOR LAYOUT OPTIMIZATION WITH MULTIPLE PRI...
- Publication number 20090158223
- Publication date Jun 18, 2009
- International Business Machines Corporation
- Michael S. Gray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OBTAINING A FEASIBLE INTEGER SOLUTION IN A HIERARCHICAL CIRCUIT LAY...
- Publication number 20090031259
- Publication date Jan 29, 2009
- Michael S. Gray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VLSI ARTWORK LEGALIZATION FOR HIERARCHICAL DESIGNS WITH MULTIPLE GR...
- Publication number 20080313577
- Publication date Dec 18, 2008
- International Business Machines Corporation
- Xiaoping TANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM TO REDISTRIBUTE WHITE SPACE FOR MINIMIZING WIRE L...
- Publication number 20080046854
- Publication date Feb 21, 2008
- International Business Machines Corporation
- Xiaoping Tang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VLSI ARTWORK LEGALIZATION FOR HIERARCHICAL DESIGNS WITH MULTIPLE GR...
- Publication number 20070240088
- Publication date Oct 11, 2007
- Xiaoping Tang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and system to redistribute white space for minimizing wire l...
- Publication number 20060156265
- Publication date Jul 13, 2006
- International Business Machines Corporation
- Xiaoping Tang
- G06 - COMPUTING CALCULATING COUNTING

Xiaoping Tang

Person

Patents Grantslast 30 patents

Layout decomposition method and apparatus for multiple patterning l...

Relative ordering circuit synthesis

Systems and methods for fixing pin mismatch in layout migration

Parallel solving of layout optimization

Decomposing layout for triple patterning lithography

Structural migration of integrated circuit layout

Methods to obtain a feasible integer solution in a hierarchical cir...

Handling two-dimensional constraints in integrated circuit layout

VLSI artwork legalization for hierarchical designs with multiple gr...

Method and system to redistribute white space for minimizing wire l...

Adaptive weighting method for layout optimization with multiple pri...

Obtaining a feasible integer solution in a hierarchical circuit lay...

VLSI artwork legalization for hierarchical designs with multiple gr...

Method and system to redistribute white space for minimizing wire l...

Patents Applicationslast 30 patents

SYSTEMS AND METHODS FOR FIXING PIN MISMATCH IN LAYOUT MIGRATION

RELATIVE ORDERING CIRCUIT SYNTHESIS

STRUCTURAL MIGRATION OF INTEGRATED CIRCUIT LAYOUT

PARALLEL SOLVING OF LAYOUT OPTIMIZATION

LAYOUT DECOMPOSITION METHOD AND APPARATUS FOR MULTIPLE PATTERNING L...

HANDLING TWO-DIMENSIONAL CONSTRAINTS IN INTEGRATED CIRCUIT LAYOUT

METHODS TO OBTAIN A FEASIBLE INTEGER SOLUTION IN A HIERARCHICAL CIR...

ADAPTIVE WEIGHTING METHOD FOR LAYOUT OPTIMIZATION WITH MULTIPLE PRI...

OBTAINING A FEASIBLE INTEGER SOLUTION IN A HIERARCHICAL CIRCUIT LAY...

VLSI ARTWORK LEGALIZATION FOR HIERARCHICAL DESIGNS WITH MULTIPLE GR...

METHOD AND SYSTEM TO REDISTRIBUTE WHITE SPACE FOR MINIMIZING WIRE L...

VLSI ARTWORK LEGALIZATION FOR HIERARCHICAL DESIGNS WITH MULTIPLE GR...

Method and system to redistribute white space for minimizing wire l...