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Xiaoqun Du
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New Providence, NJ, US
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last 30 patents
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Patent Grant
Temporal decomposition for design and verification
Patent number
8,418,101
Issue date
Apr 9, 2013
Cadence Designs Systems, Inc.
Andreas Kuehlmann
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Temporal decomposition for design and verification
Patent number
8,413,090
Issue date
Apr 2, 2013
Cadence Design Systems, Inc.
Andreas Kuehlmann
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Temporal decomposition for design and verification
Patent number
7,900,173
Issue date
Mar 1, 2011
Cadence Design Systems, Inc.
Andreas Kuehlmann
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Coverage metric and coverage computation for verification based on...
Patent number
7,712,059
Issue date
May 4, 2010
Cadence Design Systems, Inc.
Xiaoqun Du
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Temporal decomposition for design and verification
Patent number
7,596,770
Issue date
Sep 29, 2009
Cadence Design Systems, Inc.
Andreas Kuehlmann
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Method and system for verifying circuit designs through propagation...
Patent number
7,444,274
Issue date
Oct 28, 2008
Cadence Design Systems, Inc.
Manu Chopra
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Coverage metric and coverage computation for verification based on...
Patent number
7,181,708
Issue date
Feb 20, 2007
Cadence Design Systems, Inc.
Xiaoqun Du
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Method and system for partitioning an integrated circuit design
Patent number
7,047,510
Issue date
May 16, 2006
Cadence Design Systems, Inc.
Manu Chopra
G06 - COMPUTING CALCULATING COUNTING