Xiaorong Morrow

Person

Portland, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method and apparatus for forming metal-metal oxide etch stop/barrie...
- Patent number 8,299,617
- Issue date Oct 30, 2012
- Intel Corporation
- Xiaorong Morrow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for forming metal-metal oxide etch stop/barrie...
- Patent number 7,727,892
- Issue date Jun 1, 2010
- Intel Corporation
- Xiaorong Morrow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Sealing porous dielectrics with silane coupling reagents
- Patent number 7,456,490
- Issue date Nov 25, 2008
- Intel Corporation
- Grant Kloster
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Metal-metal oxide etch stop/barrier for integrated circuit intercon...
- Patent number 7,339,271
- Issue date Mar 4, 2008
- Intel Corporation
- Xiaorong Morrow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Sealing porous dielectrics with silane coupling reagents
- Patent number 7,122,481
- Issue date Oct 17, 2006
- Intel Corporation
- Grant Kloster
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Surface alteration of metal interconnect in integrated circuits for...
- Patent number 6,794,755
- Issue date Sep 21, 2004
- Intel Corporation
- Jose A. Maiz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device having a dual damascene interconnect spaced fr...
- Patent number 6,661,094
- Issue date Dec 9, 2003
- Intel Corporation
- Patrick Morrow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making a semiconductor device having a dual damascene int...
- Patent number 6,448,177
- Issue date Sep 10, 2002
- Intle Corporation
- Patrick Morrow
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
METHOD AND APPARATUS FOR FORMING METAL-METAL OXIDE ETCH STOP/BARRIE...
- Publication number 20100219529
- Publication date Sep 2, 2010
- Xiaorong Morrow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Sealing porous dielectrics with silane coupling reagents
- Publication number 20070066079
- Publication date Mar 22, 2007
- Grant Kloster
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Sealing porous dielectrics with silane coupling reagents
- Publication number 20050020074
- Publication date Jan 27, 2005
- Grant Kloster
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method and apparatus for forming metal-metal oxide etch stop/barrie...
- Publication number 20040224515
- Publication date Nov 11, 2004
- Xiaorong Morrow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Low-K dielectric structure and method
- Publication number 20040102031
- Publication date May 27, 2004
- Grant M. Kloster
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method and apparatus for forming metal-metal oxide etch stop/barrie...
- Publication number 20040058547
- Publication date Mar 25, 2004
- Xiaorong Morrow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
A METHOD OF FORMING SURFACE ALTERATION OF METAL INTERCONNECT IN INT...
- Publication number 20040056366
- Publication date Mar 25, 2004
- Jose A. Maiz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Surface alteration of metal interconnect in integrated circuits for...
- Publication number 20040056329
- Publication date Mar 25, 2004
- Jose A. Maiz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF MAKING A SEMICONDUCTOR DEVICE HAVING A DUAL DAMASCENE INT...
- Publication number 20020140104
- Publication date Oct 3, 2002
- Patrick Morrow
- H01 - BASIC ELECTRIC ELEMENTS

Xiaorong Morrow

Person

Patents Grantslast 30 patents

Method and apparatus for forming metal-metal oxide etch stop/barrie...

Method and apparatus for forming metal-metal oxide etch stop/barrie...

Sealing porous dielectrics with silane coupling reagents

Metal-metal oxide etch stop/barrier for integrated circuit intercon...

Sealing porous dielectrics with silane coupling reagents

Surface alteration of metal interconnect in integrated circuits for...

Semiconductor device having a dual damascene interconnect spaced fr...

Method of making a semiconductor device having a dual damascene int...

Patents Applicationslast 30 patents

METHOD AND APPARATUS FOR FORMING METAL-METAL OXIDE ETCH STOP/BARRIE...

Sealing porous dielectrics with silane coupling reagents

Sealing porous dielectrics with silane coupling reagents

Method and apparatus for forming metal-metal oxide etch stop/barrie...

Low-K dielectric structure and method

Method and apparatus for forming metal-metal oxide etch stop/barrie...

A METHOD OF FORMING SURFACE ALTERATION OF METAL INTERCONNECT IN INT...

Surface alteration of metal interconnect in integrated circuits for...

METHOD OF MAKING A SEMICONDUCTOR DEVICE HAVING A DUAL DAMASCENE INT...