Xijiang Lin

Person

West Linn, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Library cell modeling for transistor-level test pattern generation
- Patent number 11,635,462
- Issue date Apr 25, 2023
- SIEMENS INDUSTRY SOFTWARE INC.
- Xijiang Lin
- G01 - MEASURING TESTING
Information Patent Grant
Deterministic test pattern generation for designs with timing excep...
- Patent number 10,977,400
- Issue date Apr 13, 2021
- Mentor Graphics Corporation
- Wu-Tung Cheng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Timing-aware test generation and fault simulation
- Patent number 10,509,073
- Issue date Dec 17, 2019
- Mentor Graphics Corporation
- Xijiang Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scan cell selection for partial scan designs
- Patent number 10,372,855
- Issue date Aug 6, 2019
- Mentor Graphics Corporation
- Xijiang Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Transition test generation for detecting cell internal defects
- Patent number 10,222,420
- Issue date Mar 5, 2019
- Mentor Graphics Corporation
- Xijiang Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Timing-aware test generation and fault simulation
- Patent number 9,720,040
- Issue date Aug 1, 2017
- Mentor Graphics Corporation
- Xijiang Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Logic built-in self-test with high test coverage and low switching...
- Patent number 9,568,552
- Issue date Feb 14, 2017
- Mentor Graphics Corporation
- Xijiang Lin
- G01 - MEASURING TESTING
Information Patent Grant
Identification of power sensitive scan cells
- Patent number 9,501,589
- Issue date Nov 22, 2016
- Mentor Graphics Corporation
- Xijiang Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic shift for test pattern compression
- Patent number 9,335,374
- Issue date May 10, 2016
- Mentor Graphics Corporation
- Xijiang Lin
- G01 - MEASURING TESTING
Information Patent Grant
Timing-aware test generation and fault simulation
- Patent number 9,086,454
- Issue date Jul 21, 2015
- Mentor Graphics Corporation
- Xijiang Lin
- G01 - MEASURING TESTING
Information Patent Grant
Test data volume reduction based on test cube properties
- Patent number 8,996,941
- Issue date Mar 31, 2015
- Mentor Graphics Corporation
- Xijiang Lin
- G01 - MEASURING TESTING
Information Patent Grant
Scan cell use with reduced power consumption
- Patent number 8,890,563
- Issue date Nov 18, 2014
- Mentor Graphics Corporation
- Xijiang Lin
- G01 - MEASURING TESTING
Information Patent Grant
Timing-aware test generation and fault simulation
- Patent number 8,560,906
- Issue date Oct 15, 2013
- Mentor Graphics Corporation
- Xijiang Lin
- G01 - MEASURING TESTING
Information Patent Grant
At-speed scan testing with controlled switching activity
- Patent number 8,499,209
- Issue date Jul 30, 2013
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Grant
Low power scan testing techniques and apparatus
- Patent number 8,290,738
- Issue date Oct 16, 2012
- Mentor Graphics Corporation
- Xijiang Lin
- G01 - MEASURING TESTING
Information Patent Grant
Timing-aware test generation and fault simulation
- Patent number 8,051,352
- Issue date Nov 1, 2011
- Mentor Graphics Corporation
- Xijiang Lin
- G01 - MEASURING TESTING
Information Patent Grant
Low power scan testing techniques and apparatus
- Patent number 7,925,465
- Issue date Apr 12, 2011
- Mentor Graphics Corporation
- Xijiang Lin
- G01 - MEASURING TESTING
Information Patent Grant
Test generation methods for reducing power dissipation and supply c...
- Patent number 7,865,792
- Issue date Jan 4, 2011
- Mentor Graphics Corporation
- Xijiang Lin
- G01 - MEASURING TESTING
Information Patent Grant
Test generation methods for reducing power dissipation and supply c...
- Patent number 7,685,491
- Issue date Mar 23, 2010
- Xijiang Lin
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
LIBRARY CELL MODELING FOR TRANSISTOR-LEVEL TEST PATTERN GENERATION
- Publication number 20220065929
- Publication date Mar 3, 2022
- Mentor Graphics Corporation
- Xijiang Lin
- G01 - MEASURING TESTING
Information Patent Application
DETERMINISTIC TEST PATTERN GENERATION FOR DESIGNS WITH TIMING EXCEP...
- Publication number 20200410065
- Publication date Dec 31, 2020
- Mentor Graphics Corporation
- Wu-Tung Cheng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TIMING-AWARE TEST GENERATION AND FAULT SIMULATION
- Publication number 20180045780
- Publication date Feb 15, 2018
- Mentor Graphics Corporation
- Xijiang Lin
- G01 - MEASURING TESTING
Information Patent Application
TRANSITION TEST GENERATION FOR DETECTING CELL INTERNAL DEFECTS
- Publication number 20170193155
- Publication date Jul 6, 2017
- Mentor Graphics Corporation
- Xijiang Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TIMING-AWARE TEST GENERATION AND FAULT SIMULATION
- Publication number 20150323600
- Publication date Nov 12, 2015
- Mentor Graphics Corporation
- Xijiang Lin
- G01 - MEASURING TESTING
Information Patent Application
Scan Cell Selection For Partial Scan Designs
- Publication number 20150248515
- Publication date Sep 3, 2015
- Mentor Graphics Corporation
- Xijiang Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Dynamic Shift For Test Pattern Compression
- Publication number 20150153410
- Publication date Jun 4, 2015
- Mentor Graphics Corporation
- Xijiang Lin
- G01 - MEASURING TESTING
Information Patent Application
IDENTIFICATION OF POWER SENSITIVE SCAN CELLS
- Publication number 20150040087
- Publication date Feb 5, 2015
- Mentor Graphics Corporation
- Xijiang Lin
- G01 - MEASURING TESTING
Information Patent Application
Logic Built-In Self-Test with High Test Coverage and Low Switching...
- Publication number 20140365840
- Publication date Dec 11, 2014
- Xijiang Lin
- G01 - MEASURING TESTING
Information Patent Application
TIMING-AWARE TEST GENERATION AND FAULT SIMULATION
- Publication number 20140047404
- Publication date Feb 13, 2014
- Mentor Graphics Corporation
- Xijiang Lin
- G01 - MEASURING TESTING
Information Patent Application
Test Data Volume Reduction Based On Test Cube Properties
- Publication number 20130332786
- Publication date Dec 12, 2013
- Xijiang Lin
- G01 - MEASURING TESTING
Information Patent Application
TIMING-AWARE TEST GENERATION AND FAULT SIMULATION
- Publication number 20120174049
- Publication date Jul 5, 2012
- Mentor Graphics Corporation
- Xijiang Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Scan Cell Use With Reduced Power Consumption
- Publication number 20120043991
- Publication date Feb 23, 2012
- Xijiang Lin
- G01 - MEASURING TESTING
Information Patent Application
LOW POWER SCAN TESTING TECHNIQUES AND APPARATUS
- Publication number 20110166818
- Publication date Jul 7, 2011
- Mentor Graphics Corporation
- Xijiang Lin
- G01 - MEASURING TESTING
Information Patent Application
At-Speed Scan Testing With Controlled Switching Activity
- Publication number 20100275077
- Publication date Oct 28, 2010
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Application
TEST GENERATION METHODS FOR REDUCING POWER DISSIPATION AND SUPPLY C...
- Publication number 20100146350
- Publication date Jun 10, 2010
- Xijiang Lin
- G01 - MEASURING TESTING
Information Patent Application
Low power scan testing techniques and apparatus
- Publication number 20080195346
- Publication date Aug 14, 2008
- Xijiang Lin
- G01 - MEASURING TESTING
Information Patent Application
Timing-aware test generation and fault simulation
- Publication number 20070288822
- Publication date Dec 13, 2007
- Xijiang Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Test generation methods for reducing power dissipation and supply c...
- Publication number 20070250749
- Publication date Oct 25, 2007
- Xijiang Lin
- G01 - MEASURING TESTING

Xijiang Lin

Person

Patents Grantslast 30 patents

Library cell modeling for transistor-level test pattern generation

Deterministic test pattern generation for designs with timing excep...

Timing-aware test generation and fault simulation

Scan cell selection for partial scan designs

Transition test generation for detecting cell internal defects

Timing-aware test generation and fault simulation

Logic built-in self-test with high test coverage and low switching...

Identification of power sensitive scan cells

Dynamic shift for test pattern compression

Timing-aware test generation and fault simulation

Test data volume reduction based on test cube properties

Scan cell use with reduced power consumption

Timing-aware test generation and fault simulation

At-speed scan testing with controlled switching activity

Low power scan testing techniques and apparatus

Timing-aware test generation and fault simulation

Low power scan testing techniques and apparatus

Test generation methods for reducing power dissipation and supply c...

Test generation methods for reducing power dissipation and supply c...

Patents Applicationslast 30 patents

LIBRARY CELL MODELING FOR TRANSISTOR-LEVEL TEST PATTERN GENERATION

DETERMINISTIC TEST PATTERN GENERATION FOR DESIGNS WITH TIMING EXCEP...

TIMING-AWARE TEST GENERATION AND FAULT SIMULATION

TRANSITION TEST GENERATION FOR DETECTING CELL INTERNAL DEFECTS

TIMING-AWARE TEST GENERATION AND FAULT SIMULATION

Scan Cell Selection For Partial Scan Designs

Dynamic Shift For Test Pattern Compression

IDENTIFICATION OF POWER SENSITIVE SCAN CELLS

Logic Built-In Self-Test with High Test Coverage and Low Switching...

TIMING-AWARE TEST GENERATION AND FAULT SIMULATION

Test Data Volume Reduction Based On Test Cube Properties

TIMING-AWARE TEST GENERATION AND FAULT SIMULATION

Scan Cell Use With Reduced Power Consumption

LOW POWER SCAN TESTING TECHNIQUES AND APPARATUS

At-Speed Scan Testing With Controlled Switching Activity

TEST GENERATION METHODS FOR REDUCING POWER DISSIPATION AND SUPPLY C...

Low power scan testing techniques and apparatus

Timing-aware test generation and fault simulation

Test generation methods for reducing power dissipation and supply c...