Yan Chong

Person

Mountain View, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Variation immune on-die voltage droop detector
- Patent number 10,162,373
- Issue date Dec 25, 2018
- Ampere Computing LLC
- Yan Chong
- G05 - CONTROLLING REGULATING
Information Patent Grant
Self-referenced on-die voltage droop detector
- Patent number 10,145,868
- Issue date Dec 4, 2018
- Ampere Computing LLC
- Yan Chong
- G01 - MEASURING TESTING
Information Patent Grant
On-die input reference voltage with self-calibrating duty cycle cor...
- Patent number 9,711,189
- Issue date Jul 18, 2017
- Altera Corporation
- Bonnie I. Wang
- G11 - INFORMATION STORAGE
Information Patent Grant
Multiple data rate interface architecture
- Patent number 9,166,589
- Issue date Oct 20, 2015
- Altera Corporation
- Philip Pan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Memory interface circuitry with improved timing margins
- Patent number 9,166,596
- Issue date Oct 20, 2015
- Altera Corporation
- Yan Chong
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit design technique for DQS enable/disable calibration
- Patent number 9,158,873
- Issue date Oct 13, 2015
- Altera Corporation
- Yan Chong
- G11 - INFORMATION STORAGE
Information Patent Grant
Input-output circuitry for integrated circuits
- Patent number 9,106,230
- Issue date Aug 11, 2015
- Altera Corporation
- Bonnie I. Wang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Digital PVT compensation for delay chain
- Patent number 9,059,716
- Issue date Jun 16, 2015
- Altera Corporation
- Pradeep Nagarajan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Methods and apparatus for clock tree phase alignment
- Patent number 8,922,264
- Issue date Dec 30, 2014
- Altera Corporation
- Yan Chong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Circuits and methods for providing clock signals
- Patent number 8,847,626
- Issue date Sep 30, 2014
- Altera Corporation
- Yan Chong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Clock structure with calibration circuitry
- Patent number 8,816,743
- Issue date Aug 26, 2014
- Altera Corporation
- Sean Shau-Tu Lu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Circuit design technique for DQS enable/disable calibration
- Patent number 8,787,097
- Issue date Jul 22, 2014
- Altera Corporation
- Yan Chong
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for minimizing skew between signals
- Patent number 8,779,754
- Issue date Jul 15, 2014
- Altera Corporation
- Yan Chong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Configurable delay circuitry with compensated delay
- Patent number 8,723,575
- Issue date May 13, 2014
- Altera Corporation
- Ee Mei Ooi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Digital PVT compensation for delay chain
- Patent number 8,680,905
- Issue date Mar 25, 2014
- Altera Corporation
- Pradeep Nagarajan
- G11 - INFORMATION STORAGE
Information Patent Grant
Write-leveling implementation in programmable logic devices
- Patent number 8,671,303
- Issue date Mar 11, 2014
- Altera Corporation
- Yan Chong
- G11 - INFORMATION STORAGE
Information Patent Grant
Duty cycle correction circuit for memory interfaces in integrated c...
- Patent number 8,624,647
- Issue date Jan 7, 2014
- Altera Corporation
- Yan Chong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High performance memory interface circuit architecture
- Patent number 8,593,195
- Issue date Nov 26, 2013
- Altera Corporation
- Joseph Huang
- G11 - INFORMATION STORAGE
Information Patent Grant
Multiple data rate interface architecture
- Patent number 8,575,957
- Issue date Nov 5, 2013
- Altera Corporation
- Philip Pan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Variation compensation circuitry for memory interface
- Patent number 8,565,034
- Issue date Oct 22, 2013
- Altera Corporation
- Sean Shau-Tu Lu
- G11 - INFORMATION STORAGE
Information Patent Grant
High-performance memory interface circuit architecture
- Patent number 8,305,121
- Issue date Nov 6, 2012
- Altera Corporation
- Joseph Huang
- G11 - INFORMATION STORAGE
Information Patent Grant
Techniques for generating PVT compensated phase offset to improve a...
- Patent number 8,237,475
- Issue date Aug 7, 2012
- Altera Corporation
- Pradeep Nagarajan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Techniques for providing multiple delay paths in a delay circuit
- Patent number 8,159,277
- Issue date Apr 17, 2012
- Altera Corporation
- Pradeep Nagarajan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Techniques for providing reduced duty cycle distortion
- Patent number 8,130,016
- Issue date Mar 6, 2012
- Altera Corporation
- Pradeep Nagarajan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Write-leveling implementation in programmable logic devices
- Patent number 8,122,275
- Issue date Feb 21, 2012
- Altera Corporation
- Yan Chong
- G11 - INFORMATION STORAGE
Information Patent Grant
Multiple data rate interface architecture
- Patent number 8,098,082
- Issue date Jan 17, 2012
- Altera Corporation
- Philip Pan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Postamble timing for DDR memories
- Patent number 7,990,783
- Issue date Aug 2, 2011
- Altera Corporation
- Philip Clarke
- G11 - INFORMATION STORAGE
Information Patent Grant
Read-leveling implementations for DDR3 applications on an FPGA
- Patent number 7,990,786
- Issue date Aug 2, 2011
- Altera Corporation
- Michael H. M. Chu
- G11 - INFORMATION STORAGE
Information Patent Grant
PVT compensated auto-calibration scheme for DDR3
- Patent number 7,983,094
- Issue date Jul 19, 2011
- Altera Corporation
- Manoj B. Roge
- G11 - INFORMATION STORAGE
Information Patent Grant
High-performance memory interface circuit architecture
- Patent number 7,969,215
- Issue date Jun 28, 2011
- Altera Corporation
- Joseph Huang
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
SELF-REFERENCED ON-DIE VOLTAGE DROOP DETECTOR
- Publication number 20170261537
- Publication date Sep 14, 2017
- APPLIED MICRO CIRCUITS CORPORATION
- Yan Chong
- G01 - MEASURING TESTING
Information Patent Application
MEMORY INTERFACE CIRCUITRY WITH IMPROVED TIMING MARGINS
- Publication number 20140145756
- Publication date May 29, 2014
- Altera Corporation
- Yan Chong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLE DATA RATE INTERFACE ARCHITECTURE
- Publication number 20140049287
- Publication date Feb 20, 2014
- Altera Corporation
- Philip Pan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
MULTIPLE DATA RATE INTERFACE ARCHITECTURE
- Publication number 20120146700
- Publication date Jun 14, 2012
- Altera Corporation
- Philip Pan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
WRITE-LEVELING IMPLEMENTATION IN PROGRAMMABLE LOGIC DEVICES
- Publication number 20120106264
- Publication date May 3, 2012
- Altera Corporation
- Yan Chong
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND APPARATUS FOR MINIMIZING SKEW BETWEEN SIGNALS
- Publication number 20110221497
- Publication date Sep 15, 2011
- Yan Chong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DUTY CYCLE CORRECTION CIRCUIT FOR MEMORY INTERFACES IN INTEGRATED C...
- Publication number 20110175657
- Publication date Jul 21, 2011
- Yan Chong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Techniques for Providing Reduced Duty Cycle Distortion
- Publication number 20110074477
- Publication date Mar 31, 2011
- Altera Corporation
- Pradeep Nagarajan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
READ-LEVELING IMPLEMENTATIONS FOR DDR3 APPLICATIONS ON AN FPGA
- Publication number 20090296503
- Publication date Dec 3, 2009
- Altera Corporation
- Michael H.M. Chu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
READ-LEVELING IMPLEMENTATIONS FOR DDR3 APPLICATIONS ON AN FPGA
- Publication number 20080291758
- Publication date Nov 27, 2008
- Altera Corporation
- Michael H.M. Chu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
WRITE-LEVELING IMPLEMENTATION IN PROGRAMMABLE LOGIC DEVICES
- Publication number 20080201597
- Publication date Aug 21, 2008
- Altera Corporation
- Yan Chong
- G11 - INFORMATION STORAGE
Information Patent Application
Read-Side Calibration for Data Interface
- Publication number 20070282555
- Publication date Dec 6, 2007
- Altera Corporation
- Yan Chong
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Write-Side Calibration for Data Interface
- Publication number 20070277071
- Publication date Nov 29, 2007
- Altera Corporation
- Yan Chong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Loop circuitry with low-pass noise filter
- Publication number 20060164139
- Publication date Jul 27, 2006
- Yan Chong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Supply voltage detection circuit
- Publication number 20050253626
- Publication date Nov 17, 2005
- Yan Chong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Programmable I/O element circuit for high speed logic devices
- Publication number 20050162187
- Publication date Jul 28, 2005
- Khai Nguyen
- A61 - MEDICAL OR VETERINARY SCIENCE HYGIENE

Person

Patents Grantslast 30 patents

Variation immune on-die voltage droop detector

Self-referenced on-die voltage droop detector

On-die input reference voltage with self-calibrating duty cycle cor...

Multiple data rate interface architecture

Memory interface circuitry with improved timing margins

Circuit design technique for DQS enable/disable calibration

Input-output circuitry for integrated circuits

Digital PVT compensation for delay chain

Methods and apparatus for clock tree phase alignment

Circuits and methods for providing clock signals

Clock structure with calibration circuitry

Circuit design technique for DQS enable/disable calibration

Method and apparatus for minimizing skew between signals

Configurable delay circuitry with compensated delay

Digital PVT compensation for delay chain

Write-leveling implementation in programmable logic devices

Duty cycle correction circuit for memory interfaces in integrated c...

High performance memory interface circuit architecture

Multiple data rate interface architecture

Variation compensation circuitry for memory interface

High-performance memory interface circuit architecture

Techniques for generating PVT compensated phase offset to improve a...

Techniques for providing multiple delay paths in a delay circuit

Techniques for providing reduced duty cycle distortion

Write-leveling implementation in programmable logic devices

Multiple data rate interface architecture

Postamble timing for DDR memories

Read-leveling implementations for DDR3 applications on an FPGA

PVT compensated auto-calibration scheme for DDR3

High-performance memory interface circuit architecture

Patents Applicationslast 30 patents

SELF-REFERENCED ON-DIE VOLTAGE DROOP DETECTOR

MEMORY INTERFACE CIRCUITRY WITH IMPROVED TIMING MARGINS

MULTIPLE DATA RATE INTERFACE ARCHITECTURE

MULTIPLE DATA RATE INTERFACE ARCHITECTURE

WRITE-LEVELING IMPLEMENTATION IN PROGRAMMABLE LOGIC DEVICES

METHOD AND APPARATUS FOR MINIMIZING SKEW BETWEEN SIGNALS

DUTY CYCLE CORRECTION CIRCUIT FOR MEMORY INTERFACES IN INTEGRATED C...

Techniques for Providing Reduced Duty Cycle Distortion

READ-LEVELING IMPLEMENTATIONS FOR DDR3 APPLICATIONS ON AN FPGA

READ-LEVELING IMPLEMENTATIONS FOR DDR3 APPLICATIONS ON AN FPGA

WRITE-LEVELING IMPLEMENTATION IN PROGRAMMABLE LOGIC DEVICES

Read-Side Calibration for Data Interface

Write-Side Calibration for Data Interface

Loop circuitry with low-pass noise filter

Supply voltage detection circuit

Programmable I/O element circuit for high speed logic devices