Yan Solihin

Person

Raleigh, NC, US

People

Patents Grantslast 30 patents

Information Patent Grant
Cache partitioning in a multicore processor
- Patent number 10,956,331
- Issue date Mar 23, 2021
- EMPIRE TECHNOLOGY DEVELOPMENT LLC
- Yan Solihin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Core prioritization for heterogeneous on-chip networks
- Patent number 10,445,131
- Issue date Oct 15, 2019
- EMPIRE TECHNOLOGY DEVELOPMENT LLC
- Yan Solihin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit switch pre-reservation in an on-chip network
- Patent number 10,445,287
- Issue date Oct 15, 2019
- EMPIRE TECHNOLOGY DEVELOPMENT LLC
- Yan Solihin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache partitioning in a multicore processor
- Patent number 10,346,308
- Issue date Jul 9, 2019
- EMPIRE TECHNOLOGY DEVELOPMENT LLC
- Yan Solihin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Increased refresh interval and energy efficiency in a DRAM
- Patent number 10,346,227
- Issue date Jul 9, 2019
- EMPIRE TECHNOLOGY DEVELOPMENT LLC
- Yan Solihin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Thread and data assignment in multi-core processors based on cache...
- Patent number 10,289,452
- Issue date May 14, 2019
- Empire Technology Development, LLC
- Yan Solihin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and systems for dynamic DRAM cache sizing
- Patent number 10,176,107
- Issue date Jan 8, 2019
- EMPIRE TECHNOLOGY DEVELOPMENT LLC
- Yan Solihin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Magnetoresistive random-access memory cache write management
- Patent number 10,152,410
- Issue date Dec 11, 2018
- EMPIRE TECHNOLOGY DEVELOPMENT LLC
- Yan Solihin
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Hardware-based array compression
- Patent number 10,007,605
- Issue date Jun 26, 2018
- EMPIRE TECHNOLOGY DEVELOPMENT LLC
- Yan Solihin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Energy-efficient dynamic dram cache sizing via selective refresh of...
- Patent number 9,990,293
- Issue date Jun 5, 2018
- EMPIRE TECHNOLOGY DEVELOPMENT LLC
- Yan Solihin
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory allocation accelerator
- Patent number 9,965,385
- Issue date May 8, 2018
- EMPIRE TECHNOLOGY DEVELOPMENT LLC
- Yan Solihin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Directory coherence for multicore processors
- Patent number 9,946,647
- Issue date Apr 17, 2018
- EMPIRE TECHNOLOGY DEVELOPMENT LLC
- Yan Solihin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data storage based on memory persistency
- Patent number 9,916,255
- Issue date Mar 13, 2018
- EMPIRE TECHNOLOGY DEVELOPMENT LLC
- Yan Solihin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Heterogeneous magnetic memory architecture
- Patent number 9,858,111
- Issue date Jan 2, 2018
- Empire Technologies Development LLC
- Yan Solihin
- G11 - INFORMATION STORAGE
Information Patent Grant
Systems and methods for modeling memory access behavior and memory...
- Patent number 9,846,627
- Issue date Dec 19, 2017
- North Carolina State University
- Yan Solihin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-granular cache coherence
- Patent number 9,772,950
- Issue date Sep 26, 2017
- EMPIRE TECHNOLOGY DEVELOPMENT LLC
- Yan Solihin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Operations related to a retransmission buffer
- Patent number 9,766,681
- Issue date Sep 19, 2017
- EMPIRE TECHNOLOGY DEVELOPMENT LLC
- Yan Solihin
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Accelerating cache state transfer on a directory-based multicore ar...
- Patent number 9,760,486
- Issue date Sep 12, 2017
- EMPIRE TECHNOLOGY DEVELOPMENT LLC
- Yan Solihin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Shared cache data movement in thread migration
- Patent number 9,710,303
- Issue date Jul 18, 2017
- EMPIRE TECHNOLOGY DEVELOPMENT LLC
- Yan Solihin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory initialization using cache state
- Patent number 9,684,603
- Issue date Jun 20, 2017
- EMPIRE TECHNOLOGY DEVELOPMENT LLC
- Yan Solihin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic router power control in multi-core processors
- Patent number 9,678,550
- Issue date Jun 13, 2017
- EMPIRE TECHNOLOGY DEVELOPMENT LLC
- Mazen Kharbutli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Thread and data assignment in multi-core processors based on cache...
- Patent number 9,632,832
- Issue date Apr 25, 2017
- EMPIRE TECHNOLOGY DEVELOPMENT LLC
- Yan Solihin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache partitioning in a multicore processor
- Patent number 9,612,961
- Issue date Apr 4, 2017
- EMPIRE TECHNOLOGY DEVELOPMENT LLC
- Yan Solihin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Increased refresh interval and energy efficiency in a DRAM
- Patent number 9,564,202
- Issue date Feb 7, 2017
- EMPIRE TECHNOLOGY DEVELOPMENT LLC
- Yan Solihin
- G11 - INFORMATION STORAGE
Information Patent Grant
Performance and energy efficiency while using large pages
- Patent number 9,552,295
- Issue date Jan 24, 2017
- EMPIRE TECHNOLOGY DEVELOPMENT LLC
- Yan Solihin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Detecting unidirectional resistance drift errors in a multilevel ce...
- Patent number 9,501,350
- Issue date Nov 22, 2016
- EMPIRE TECHNOLOGY DEVELOPMENT LLC
- Yan Solihin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hybrid routers in multicore architectures
- Patent number 9,473,426
- Issue date Oct 18, 2016
- EMPIRE TECHNOLOGY DEVELOPMENT LLC
- Yan Solihin
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Resource allocation in multi-core architectures
- Patent number 9,471,381
- Issue date Oct 18, 2016
- EMPIRE TECHNOLOGY DEVELOPMENT LLC
- Yan Solihin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory allocation accelerator
- Patent number 9,465,729
- Issue date Oct 11, 2016
- EMPIRE TECHNOLOGY DEVELOPMENT LLC
- Yan Solihin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Directory error correction in multi-core processor architectures
- Patent number 9,411,693
- Issue date Aug 9, 2016
- EMPIRE TECHNOLOGY DEVELOPMENT LLC
- Yan Solihin
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
CACHE PARTITIONING IN A MULTICORE PROCESSOR
- Publication number 20190370175
- Publication date Dec 5, 2019
- EMPIRE TECHNOLOGY DEVELOPMENT LLC
- Yan Solihin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
THREAD AND DATA ASSIGNMENT IN MULTI-CORE PROCESSORS
- Publication number 20170228259
- Publication date Aug 10, 2017
- EMPIRE TECHNOLOGY DEVELOPMENT LLC
- Yan Solihin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE PARTITIONING IN A MULTICORE PROCESSOR
- Publication number 20170206163
- Publication date Jul 20, 2017
- EMPIRE TECHNOLOGY DEVELOPMENT LLC
- Yan Solihin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ENERGY-EFFICIENT DYNAMIC DRAM CACHE SIZING
- Publication number 20170132144
- Publication date May 11, 2017
- EMPIRE TECHNOLOGY DEVELOPMENT LLC
- Yan Solihin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INCREASED REFRESH INTERVAL AND ENERGY EFFICIENCY IN A DRAM
- Publication number 20170116058
- Publication date Apr 27, 2017
- EMPIRE TECHNOLOGY DEVELOPMENT LLC
- Yan Solihin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CORE PRIORITIZATION FOR HETEROGENEOUS ON-CHIP NETWORKS
- Publication number 20170046198
- Publication date Feb 16, 2017
- EMPIRE TECHNOLOGY DEVELOPMENT LLC
- Yan Solihin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DIRECTORY COHERENCE FOR MULTICORE PROCESSORS
- Publication number 20170046263
- Publication date Feb 16, 2017
- EMPIRE TECHNOLOGY DEVELOPMENT LLC
- Yan Solihin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY ALLOCATION ACCELLERATOR
- Publication number 20170004079
- Publication date Jan 5, 2017
- EMPIRE TECHNOLOGY DEVELOPMENT LLC
- Yan Solihin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
THREAD AND DATA ASSIGNMENT IN MULTI-CORE PROCESSORS
- Publication number 20160253212
- Publication date Sep 1, 2016
- EMPIRE TECHNOLOGY DEVELOPMENT LLC
- Yan Solihin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR MODELING MEMORY ACCESS BEHAVIOR AND MEMORY...
- Publication number 20160239212
- Publication date Aug 18, 2016
- North Carolina State University
- Yan Solihin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY INITIALIZATION USING CACHE STATE
- Publication number 20160217080
- Publication date Jul 28, 2016
- EMPIRE TECHNOLOGY DEVELOPMENT LLC
- Yan Solihin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ACCELERATING CACHE STATE TRANSFER ON A DIRECTORY-BASED MULTICORE AR...
- Publication number 20160210229
- Publication date Jul 21, 2016
- EMPIRE TECHNOLOGY DEVELOPMENT LLC
- Yan Solihin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA STORAGE BASED ON MEMORY PERSISTENCY
- Publication number 20160170897
- Publication date Jun 16, 2016
- EMPIRE TECHNOLOGY DEVELOPMENT LLC
- Yan Solihin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HARDWARE-BASED ARRAY COMPRESSION
- Publication number 20160117257
- Publication date Apr 28, 2016
- EMPIRE TECHNOLOGY DEVELOPMENT LLC
- Yan Solihin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Detecting Unidirectional Resistance Drift Errors In A Multilevel Ce...
- Publication number 20160085617
- Publication date Mar 24, 2016
- EMPIRE TECHNOLOGY DEVELOPMENT LLC
- Yan Solihin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ENERGY-EFFICIENT DYNAMIC DRAM CACHE SIZING
- Publication number 20160048451
- Publication date Feb 18, 2016
- EMPIRE TECHNOLOGY DEVELOPMENT LLC
- Yan Solihin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MAGNETORESISTIVE RANDOM-ACCESS MEMORY CACHE WRITE MANAGEMENT
- Publication number 20160048447
- Publication date Feb 18, 2016
- EMPIRE TECHNOLOGY DEVELOPMENT LLC
- Yan Solihin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC ROUTER POWER CONTROL IN MULTI-CORE PROCESSORS
- Publication number 20160026227
- Publication date Jan 28, 2016
- EMPIRE TECHNOLOGY DEVELOPMENT LLC
- MAZEN KHARBUTLI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HETEROGENEOUS MAGNETIC MEMORY ARCHITECTURE
- Publication number 20150371694
- Publication date Dec 24, 2015
- EMPIRE TECHNOLOGY DEVELOPMENT LLC
- Yan Solihin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SELECTIVE RETRANSMISSION IN NEAR THRESHOLD NETWORK ON CHIP
- Publication number 20150362975
- Publication date Dec 17, 2015
- EMPIRE TECHNOLOGY DEVELOPMENT LLC
- Yan SOLIHIN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CIRCUIT SWITCH PRE-RESERVATION IN AN ON-CHIP NETWORK
- Publication number 20150331831
- Publication date Nov 19, 2015
- EMPIRE TECHNOLOGY DEVELOPMENT LLC
- Yan SOLIHIN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-GRANULAR CACHE COHERENCE
- Publication number 20150286577
- Publication date Oct 8, 2015
- EMPIRE TECHNOLOGY DEVELOPMENT LLC
- Yan Solihin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INCREASED REFRESH INTERVAL AND ENERGY EFFICIENCY IN A DRAM
- Publication number 20150243340
- Publication date Aug 27, 2015
- EMPIRE TECHNOLOGY DEVELOPMENT LLC
- Yan Solihin
- G11 - INFORMATION STORAGE
Information Patent Application
BALANCED PROCESSING USING HETEROGENEOUS CORES
- Publication number 20150242240
- Publication date Aug 27, 2015
- EMPIRE TECHNOLOGY DEVELOPMENT LLC
- Yan Solihin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE COHERENCE DIRECTORY IN MULTI-PROCESSOR ARCHITECTURES
- Publication number 20150220437
- Publication date Aug 6, 2015
- EMPIRE TECHNOLOGY DEVELOPMENT LLC
- Yan Solihin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RESOURCE ALLOCATION IN MULTI-CORE ARCHITECTURES
- Publication number 20150186186
- Publication date Jul 2, 2015
- EMPIRE TECHNOLOGY DEVELOPMENT LLC
- Yan Solihin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE PARTITIONING IN A MULTICORE PROCESSOR
- Publication number 20150127912
- Publication date May 7, 2015
- Yan Solihin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SHARED CACHE DATA MOVEMENT IN THREAD MIGRATION
- Publication number 20140366030
- Publication date Dec 11, 2014
- Empire Technology Development, LLC
- Yan Solihin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HYBRID ROUTERS IN MULTICORE ARCHITECTURES
- Publication number 20140286179
- Publication date Sep 25, 2014
- Empire Technology Development, LLC
- Yan Solihin
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
HETEROGENEOUS ROUTER CLOCK ASSIGNMENT AND PACKET ROUTING
- Publication number 20140286191
- Publication date Sep 25, 2014
- Empire Technology Development, LLC
- Yan Solihin
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Yan Solihin

Person

Patents Grantslast 30 patents

Cache partitioning in a multicore processor

Core prioritization for heterogeneous on-chip networks

Circuit switch pre-reservation in an on-chip network

Cache partitioning in a multicore processor

Increased refresh interval and energy efficiency in a DRAM

Thread and data assignment in multi-core processors based on cache...

Methods and systems for dynamic DRAM cache sizing

Magnetoresistive random-access memory cache write management

Hardware-based array compression

Energy-efficient dynamic dram cache sizing via selective refresh of...

Memory allocation accelerator

Directory coherence for multicore processors

Data storage based on memory persistency

Heterogeneous magnetic memory architecture

Systems and methods for modeling memory access behavior and memory...

Multi-granular cache coherence

Operations related to a retransmission buffer

Accelerating cache state transfer on a directory-based multicore ar...

Shared cache data movement in thread migration

Memory initialization using cache state

Dynamic router power control in multi-core processors

Thread and data assignment in multi-core processors based on cache...

Cache partitioning in a multicore processor

Increased refresh interval and energy efficiency in a DRAM

Performance and energy efficiency while using large pages

Detecting unidirectional resistance drift errors in a multilevel ce...

Hybrid routers in multicore architectures

Resource allocation in multi-core architectures

Memory allocation accelerator

Directory error correction in multi-core processor architectures

Patents Applicationslast 30 patents

CACHE PARTITIONING IN A MULTICORE PROCESSOR

THREAD AND DATA ASSIGNMENT IN MULTI-CORE PROCESSORS

CACHE PARTITIONING IN A MULTICORE PROCESSOR

ENERGY-EFFICIENT DYNAMIC DRAM CACHE SIZING

INCREASED REFRESH INTERVAL AND ENERGY EFFICIENCY IN A DRAM

CORE PRIORITIZATION FOR HETEROGENEOUS ON-CHIP NETWORKS

DIRECTORY COHERENCE FOR MULTICORE PROCESSORS

MEMORY ALLOCATION ACCELLERATOR

THREAD AND DATA ASSIGNMENT IN MULTI-CORE PROCESSORS

SYSTEMS AND METHODS FOR MODELING MEMORY ACCESS BEHAVIOR AND MEMORY...

MEMORY INITIALIZATION USING CACHE STATE

ACCELERATING CACHE STATE TRANSFER ON A DIRECTORY-BASED MULTICORE AR...

DATA STORAGE BASED ON MEMORY PERSISTENCY

HARDWARE-BASED ARRAY COMPRESSION

Detecting Unidirectional Resistance Drift Errors In A Multilevel Ce...

ENERGY-EFFICIENT DYNAMIC DRAM CACHE SIZING

MAGNETORESISTIVE RANDOM-ACCESS MEMORY CACHE WRITE MANAGEMENT

DYNAMIC ROUTER POWER CONTROL IN MULTI-CORE PROCESSORS

HETEROGENEOUS MAGNETIC MEMORY ARCHITECTURE

SELECTIVE RETRANSMISSION IN NEAR THRESHOLD NETWORK ON CHIP

CIRCUIT SWITCH PRE-RESERVATION IN AN ON-CHIP NETWORK

MULTI-GRANULAR CACHE COHERENCE

INCREASED REFRESH INTERVAL AND ENERGY EFFICIENCY IN A DRAM

BALANCED PROCESSING USING HETEROGENEOUS CORES

CACHE COHERENCE DIRECTORY IN MULTI-PROCESSOR ARCHITECTURES

RESOURCE ALLOCATION IN MULTI-CORE ARCHITECTURES

CACHE PARTITIONING IN A MULTICORE PROCESSOR

SHARED CACHE DATA MOVEMENT IN THREAD MIGRATION

HYBRID ROUTERS IN MULTICORE ARCHITECTURES

HETEROGENEOUS ROUTER CLOCK ASSIGNMENT AND PACKET ROUTING