Yang ZHOU

Person

Hsinchu, TW

People

Patents Grantslast 30 patents

Information Patent Grant
Method for forming a timing circuit arrangements for flip-flops
- Patent number 11,942,945
- Issue date Mar 26, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Huaixin Xian
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Shared well structure, layout, and method
- Patent number 11,876,088
- Issue date Jan 16, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Yang Zhou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit device
- Patent number 11,862,621
- Issue date Jan 2, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Huaixin Xian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit arrangements having reduced dependency on layout environment
- Patent number 11,699,015
- Issue date Jul 11, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd
- Huaixin Xian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Timing circuit arrangements for flip-flops
- Patent number 11,469,743
- Issue date Oct 11, 2022
- Taiwan Semiconductor Manufacturing Company, Ltd
- Huaixin Xian
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
METHOD FOR FORMING A TIMING CIRCUIT ARRANGEMENTS FOR FLIP-FLOPS
- Publication number 20240267036
- Publication date Aug 8, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Huaixin XIAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SHARED WELL STRUCTURE MANUFACTURING METHOD
- Publication number 20240088128
- Publication date Mar 14, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Yang ZHOU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT DEVICE
- Publication number 20240088129
- Publication date Mar 14, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Huaixin XIAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CIRCUIT ARRANGEMENTS HAVING REDUCED DEPENDENCY ON LAYOUT ENVIRONMENT
- Publication number 20230359798
- Publication date Nov 9, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Huaixin XIAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CIRCUIT ARRANGEMENTS HAVING REDUCED DEPENDENCY ON LAYOUT ENVIRONMENT
- Publication number 20230004702
- Publication date Jan 5, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Huaixin XIAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SHARED WELL STRUCTURE, LAYOUT, AND METHOD
- Publication number 20220399326
- Publication date Dec 15, 2022
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Yang ZHOU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT DEVICE
- Publication number 20220375920
- Publication date Nov 24, 2022
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Huaixin XIAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR FORMING A TIMING CIRCUIT ARRANGEMENTS FOR FLIP-FLOPS
- Publication number 20220360253
- Publication date Nov 10, 2022
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Huaixin XIAN
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
TIMING CIRCUIT ARRANGEMENTS FOR FLIP-FLOPS
- Publication number 20220321108
- Publication date Oct 6, 2022
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Huaixin XIAN
- H03 - BASIC ELECTRONIC CIRCUITRY

Person

Patents Grantslast 30 patents

Method for forming a timing circuit arrangements for flip-flops

Shared well structure, layout, and method

Integrated circuit device

Circuit arrangements having reduced dependency on layout environment

Timing circuit arrangements for flip-flops

Patents Applicationslast 30 patents

METHOD FOR FORMING A TIMING CIRCUIT ARRANGEMENTS FOR FLIP-FLOPS

SHARED WELL STRUCTURE MANUFACTURING METHOD

INTEGRATED CIRCUIT DEVICE

CIRCUIT ARRANGEMENTS HAVING REDUCED DEPENDENCY ON LAYOUT ENVIRONMENT

CIRCUIT ARRANGEMENTS HAVING REDUCED DEPENDENCY ON LAYOUT ENVIRONMENT

SHARED WELL STRUCTURE, LAYOUT, AND METHOD

INTEGRATED CIRCUIT DEVICE

METHOD FOR FORMING A TIMING CIRCUIT ARRANGEMENTS FOR FLIP-FLOPS

TIMING CIRCUIT ARRANGEMENTS FOR FLIP-FLOPS