Yanhua Yi

Person

Cupertino, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Emulation performance analysis using abstract timing graph represen...
- Patent number 11,966,677
- Issue date Apr 23, 2024
- Synopsys, Inc.
- Melvyn Goveas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Machine learning delay estimation for emulation systems
- Patent number 11,860,227
- Issue date Jan 2, 2024
- Synopsys, Inc.
- Yanhua Yi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock placement for programmable logic devices
- Patent number 9,672,307
- Issue date Jun 6, 2017
- Lattice Semiconductor Corporation
- Chih-Chung Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bus-based clock to out path optimization
- Patent number 9,390,220
- Issue date Jul 12, 2016
- LATTICE SEMICONDUCTOR CORPORATION
- Yanhua Yi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Holdtime correction using input/output block delay
- Patent number 9,330,217
- Issue date May 3, 2016
- LATTICE SEMICONDUCTOR CORPORATION
- Yanhua Yi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-priority placement for configuring programmable logic devices
- Patent number 8,181,139
- Issue date May 15, 2012
- Lattice Semicondutor Corporation
- Xiaotao Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scan chain systems and methods for programmable logic devices
- Patent number 7,757,198
- Issue date Jul 13, 2010
- Lattice Semiconductor Corporation
- Jun Zhao
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Integrating Machine Learning Delay Estimation in FPGA-Based Emulati...
- Publication number 20240094290
- Publication date Mar 21, 2024
- Synopsys, Inc.
- Yanhua Yi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MACHINE LEARNING DELAY ESTIMATION FOR EMULATION SYSTEMS
- Publication number 20220187367
- Publication date Jun 16, 2022
- Synopsys, Inc.
- Yanhua Yi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CLOCK PLACEMENT FOR PROGRAMMABLE LOGIC DEVICES
- Publication number 20160321385
- Publication date Nov 3, 2016
- Lattice Semiconductor Corporation
- Chih-Chung Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BUS-BASED CLOCK TO OUT PATH OPTIMIZATION
- Publication number 20160026746
- Publication date Jan 28, 2016
- Lattice Semiconductor Corporation
- Yanhua Yi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CLOCK TO OUT PATH OPTIMIZATION
- Publication number 20160026745
- Publication date Jan 28, 2016
- Lattice Semiconductor Corporation
- Yanhua Yi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HOLDTIME CORRECTION USING INPUT/OUTPUT BLOCK DELAY
- Publication number 20150370941
- Publication date Dec 24, 2015
- Lattice Semiconductor Corporation
- Yanhua Yi
- G06 - COMPUTING CALCULATING COUNTING

Person

Patents Grantslast 30 patents

Emulation performance analysis using abstract timing graph represen...

Machine learning delay estimation for emulation systems

Clock placement for programmable logic devices

Bus-based clock to out path optimization

Holdtime correction using input/output block delay

Multi-priority placement for configuring programmable logic devices

Scan chain systems and methods for programmable logic devices

Patents Applicationslast 30 patents

Integrating Machine Learning Delay Estimation in FPGA-Based Emulati...

MACHINE LEARNING DELAY ESTIMATION FOR EMULATION SYSTEMS

CLOCK PLACEMENT FOR PROGRAMMABLE LOGIC DEVICES

BUS-BASED CLOCK TO OUT PATH OPTIMIZATION

CLOCK TO OUT PATH OPTIMIZATION

HOLDTIME CORRECTION USING INPUT/OUTPUT BLOCK DELAY