Yaniv Maroz

Person

TEL AVIV, IL

People

Patents Grantslast 30 patents

Information Patent Grant
Phase shifter self-test
- Patent number 11,573,290
- Issue date Feb 7, 2023
- AyDee Kay LLC
- Tom Heller
- G01 - MEASURING TESTING
Information Patent Grant
Integrated circuit design with optimized timing constraint configur...
- Patent number 10,831,958
- Issue date Nov 10, 2020
- International Business Machines Corporation
- Ofer Geva
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit generation based on zero wire load assertions
- Patent number 10,657,211
- Issue date May 19, 2020
- International Business Machines Corporation
- Limor Plotkin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Estimating timing convergence using assertion comparisons
- Patent number 10,572,613
- Issue date Feb 25, 2020
- International Business Machines Corporation
- Ofer Geva
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Modifying a circuit design
- Patent number 10,568,203
- Issue date Feb 18, 2020
- International Business Machines Corporation
- Ofer Geva
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Modifying a circuit design based on pre-routed top level design
- Patent number 10,546,092
- Issue date Jan 28, 2020
- International Business Machines Corporation
- Ido Geldman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Estimating timing convergence using assertion comparisons
- Patent number 10,325,045
- Issue date Jun 18, 2019
- International Business Machines Corporation
- Ofer Geva
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
PHASE SHIFTER SELF-TEST
- Publication number 20220003839
- Publication date Jan 6, 2022
- Semiconductor Components Industries, LLC
- Tom HELLER
- G01 - MEASURING TESTING
Information Patent Application
INTEGRATED CIRCUIT DESIGN WITH OPTIMIZED TIMING CONSTRAINT CONFIGUR...
- Publication number 20200104452
- Publication date Apr 2, 2020
- International Business Machines Corporation
- OFER GEVA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CIRCUIT GENERATION BASED ON ZERO WIRE LOAD ASSERTIONS
- Publication number 20190325102
- Publication date Oct 24, 2019
- International Business Machines Corporation
- Limor Plotkin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MODIFYING A CIRCUIT DESIGN BASED ON PRE-ROUTED TOP LEVEL DESIGN
- Publication number 20190188351
- Publication date Jun 20, 2019
- International Business Machines Corporation
- Ido Geldman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Modifying a Circuit Design
- Publication number 20180359851
- Publication date Dec 13, 2018
- International Business Machines Corporation
- Ofer Geva
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Modifying a Circuit Design
- Publication number 20180359852
- Publication date Dec 13, 2018
- International Business Machines Corporation
- Ofer Geva
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ESTIMATING TIMING CONVERGENCE USING ASSERTION COMPARISONS
- Publication number 20180341732
- Publication date Nov 29, 2018
- International Business Machines Corporation
- Ofer Geva
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ESTIMATING TIMING CONVERGENCE USING ASSERTION COMPARISONS
- Publication number 20180341731
- Publication date Nov 29, 2018
- International Business Machines Corporation
- Ofer Geva
- G06 - COMPUTING CALCULATING COUNTING

Yaniv Maroz

Person

Patents Grantslast 30 patents

Phase shifter self-test

Integrated circuit design with optimized timing constraint configur...

Circuit generation based on zero wire load assertions

Estimating timing convergence using assertion comparisons

Modifying a circuit design

Modifying a circuit design based on pre-routed top level design

Estimating timing convergence using assertion comparisons

Patents Applicationslast 30 patents

PHASE SHIFTER SELF-TEST

INTEGRATED CIRCUIT DESIGN WITH OPTIMIZED TIMING CONSTRAINT CONFIGUR...

CIRCUIT GENERATION BASED ON ZERO WIRE LOAD ASSERTIONS

MODIFYING A CIRCUIT DESIGN BASED ON PRE-ROUTED TOP LEVEL DESIGN

Modifying a Circuit Design

Modifying a Circuit Design

ESTIMATING TIMING CONVERGENCE USING ASSERTION COMPARISONS

ESTIMATING TIMING CONVERGENCE USING ASSERTION COMPARISONS