Yannick Le Tiec

Person

Crolles, FR

People

Patents Grantslast 30 patents

Information Patent Grant
Method for manufacturing a fin MOS transistor
- Patent number 9,673,329
- Issue date Jun 6, 2017
- STMicroelectronics S.A.
- Yves Morand
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low leakage dual STI integrated circuit including FDSOI transistors
- Patent number 9,601,511
- Issue date Mar 21, 2017
- Commissariat a l'Energie Atomique et Aux Energies Alternatives
- Maud Vinet
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual STI integrated circuit including FDSOI transistors and method...
- Patent number 9,570,465
- Issue date Feb 14, 2017
- Commissariat a l'Energie Atomique et Aux Energies Alternatives
- Maud Vinet
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating microelectronic devices with isolation trenc...
- Patent number 9,437,474
- Issue date Sep 6, 2016
- Commissariat a l'Energie Atomique et aux Energies Alternative
- Laurent Grenouillet
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Defective P-N junction for backgated fully depleted silicon on insu...
- Patent number 9,373,507
- Issue date Jun 21, 2016
- GLOBALFOUNDRIES, INC.
- Kangguo Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Transistor with reduced parasitic capacitance and access resistance...
- Patent number 9,337,350
- Issue date May 10, 2016
- Commissariat a l'Energie Atomique et Aux Energies Alternatives
- Nicolas Posseme
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual channel hybrid semiconductor-on-insulator semiconductor devices
- Patent number 9,293,474
- Issue date Mar 22, 2016
- International Business Machines Corporation
- Kangguo Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for manufacturing a fin MOS transistor
- Patent number 9,236,478
- Issue date Jan 12, 2016
- STMicroelectronics S.A.
- Yves Morand
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for treating the surface of a silicon substrate
- Patent number 9,231,062
- Issue date Jan 5, 2016
- Commissariat a l'Energie Atomique et Aux Energies Alternatives
- Yannick Le Tiec
- C09 - DYES PAINTS POLISHES NATURAL RESINS ADHESIVES MISCELLANEOUS COMPOSITION...
Information Patent Grant
Method for making a semiconductor structure with a buried ground plane
- Patent number 9,214,515
- Issue date Dec 15, 2015
- Commissariat a l'Energie Atomique et Aux Energies Alternatives
- Yannick Le Tiec
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Contact isolation scheme for thin buried oxide substrate devices
- Patent number 9,105,691
- Issue date Aug 11, 2015
- International Business Machines Corporation
- Kangguo Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to prepare semi-conductor device comprising a selective etch...
- Patent number 9,076,732
- Issue date Jul 7, 2015
- Commissariat a l'Energie Atomique et Aux Energies Alternatives
- Yannick Le Tiec
- C09 - DYES PAINTS POLISHES NATURAL RESINS ADHESIVES MISCELLANEOUS COMPOSITION...
Information Patent Grant
Method for producing a field effect transistor with implantation th...
- Patent number 9,070,709
- Issue date Jun 30, 2015
- Commissariat a l'Energie Atomique et Aux Energies Alternatives
- Nicolas Posseme
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual channel hybrid semiconductor-on-insulator semiconductor devices
- Patent number 9,059,041
- Issue date Jun 16, 2015
- International Business Machines Corporation
- Kangguo Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Field effect transistor with offset counter-electrode contact
- Patent number 8,994,142
- Issue date Mar 31, 2015
- Commissariat a l'Energie Atomique et Aux Energies Alternatives
- Maud Vinet
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Microelectronic device with isolation trenches extending under an a...
- Patent number 8,987,854
- Issue date Mar 24, 2015
- Commissariat a l'Energie Atomique et Aux Energies Alternatives
- Maud Vinet
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Defective P-N junction for backgated fully depleted silicon on insu...
- Patent number 8,969,966
- Issue date Mar 3, 2015
- International Business Machines Corporation
- Kangguo Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for producing a field effect transistor with a SiGe channel...
- Patent number 8,877,618
- Issue date Nov 4, 2014
- Commissariat a l'Energie Atomique et Aux Energies Alternatives
- Laurent Grenouillet
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of producing insulation trenches in a semiconductor on insul...
- Patent number 8,735,259
- Issue date May 27, 2014
- Commissariat a l'Energie Atomique et Aux Energies Alternatives
- Yannick Le Tiec
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating a field effect device with weak junction cap...
- Patent number 8,722,499
- Issue date May 13, 2014
- Commissariat a l'Energie Atomique et Aux Energies Alternatives
- Maud Vinet
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for assembling substrates with low-temperature heat treatments
- Patent number 8,530,331
- Issue date Sep 10, 2013
- Commissariat a l'Energie Atomique
- Remi Beneyton
- C09 - DYES PAINTS POLISHES NATURAL RESINS ADHESIVES MISCELLANEOUS COMPOSITION...
Information Patent Grant
Method for making a semiconductor structure with a buried ground plane
- Patent number 8,501,588
- Issue date Aug 6, 2013
- Commissariat a l'Energie Atomique et Aux Energies Alternatives
- Yannick Le Tiec
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
METHOD FOR MANUFACTURING A FIN MOS TRANSISTOR
- Publication number 20160087092
- Publication date Mar 24, 2016
- STMicroelectronics S.A.
- Yves Morand
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DUAL STI INTEGRATED CIRCUIT INCLUDING FDSOI TRANSISTORS AND METHOD...
- Publication number 20160013205
- Publication date Jan 14, 2016
- Commissariat A L'Energie Atomique et Aux Energies Alternatives
- Maud VINET
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOW LEAKAGE DUAL STI INTEGRATED CIRCUIT INCLUDING FDSOI TRANSISTORS
- Publication number 20160013206
- Publication date Jan 14, 2016
- Commissariat A L'Energie Atomique et Aux Energies Alternatives
- Maud VINET
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FABRICATING MICROELECTRONIC DEVICES WITH ISOLATION TRENC...
- Publication number 20150294903
- Publication date Oct 15, 2015
- COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE. ALT.
- Laurent Grenouillet
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DUAL CHANNEL HYBRID SEMICONDUCTOR-ON-INSULATOR SEMICONDUCTOR DEVICES
- Publication number 20150279861
- Publication date Oct 1, 2015
- International Business Machines Corporation
- Kangguo Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEFECTIVE P-N JUNCTION FOR BACKGATED FULLY DEPLETED SILICON ON INSU...
- Publication number 20150179453
- Publication date Jun 25, 2015
- International Business Machines Corporation
- Kangguo Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DUAL CHANNEL HYBRID SEMICONDUCTOR-ON-INSULATOR SEMICONDUCTOR DEVICES
- Publication number 20150008520
- Publication date Jan 8, 2015
- International Business Machines Corporation
- Kangguo Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEFECTIVE P-N JUNCTION FOR BACKGATED FULLY DEPLETED SILICON ON INSU...
- Publication number 20140312461
- Publication date Oct 23, 2014
- International Business Machines Corporation
- Kangguo Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CONTACT ISOLATION SCHEME FOR THIN BURIED OXIDE SUBSTRATE DEVICES
- Publication number 20140302661
- Publication date Oct 9, 2014
- International Business Machines Corporation
- Kangguo Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR MANUFACTURING A FIN MOS TRANSISTOR
- Publication number 20140246723
- Publication date Sep 4, 2014
- Commissariat a I'Energie Atomique et aux Energies Alternatives
- YVES MORAND
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR PRODUCING A FIELD EFFECT TRANSISTOR WITH A SiGe CHANNEL...
- Publication number 20140127871
- Publication date May 8, 2014
- Laurent GRENOUILLET
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR PRODUCING A FIELD EFFECT TRANSISTOR WITH IMPLANTATION TH...
- Publication number 20140087524
- Publication date Mar 27, 2014
- STMicroelectronics, Inc.
- Nicolas Posseme
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MICROELECTRONIC DEVICE WITH ISOLATION TRENCHES EXTENDING UNDER AN A...
- Publication number 20140061798
- Publication date Mar 6, 2014
- COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE. ALT.
- Maud VINET
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR MAKING A SEMICONDUCTOR STRUCTURE WITH A BURIED GROUND PLANE
- Publication number 20130341649
- Publication date Dec 26, 2013
- Yannick Le Tiec
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR TREATING THE SURFACE OF A SILICON SUBSTRATE
- Publication number 20130309449
- Publication date Nov 21, 2013
- COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE. ALT.
- Yannick Le Tiec
- C09 - DYES PAINTS POLISHES NATURAL RESINS ADHESIVES MISCELLANEOUS COMPOSITION...
Information Patent Application
METHOD OF PRODUCING INSULATION TRENCHES IN A SEMICONDUCTOR ON INSUL...
- Publication number 20130189825
- Publication date Jul 25, 2013
- COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE. ALT.
- Yannick LE TIEC
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TRANSISTOR AND METHOD OF FABRICATION
- Publication number 20130161746
- Publication date Jun 27, 2013
- COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE. ALT.
- Nicolas POSSEME
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD TO PREPARE SEMI-CONDUCTOR DEVICE COMPRISING A SELECTIVE ETCH...
- Publication number 20130109191
- Publication date May 2, 2013
- Commissariat A L'Energie Atomique et Aux Energies Alternatives
- Yannick LE TIEC
- C09 - DYES PAINTS POLISHES NATURAL RESINS ADHESIVES MISCELLANEOUS COMPOSITION...
Information Patent Application
FIELD EFFECT TRANSISTOR WITH OFFSET COUNTER-ELECTRODE CONTACT
- Publication number 20120256262
- Publication date Oct 11, 2012
- Commissariat A L'Energie Atomique et Aux Energies Alternatives
- Maud VINET
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FIELD EFFECT DEVICE PROVIDED WITH A LOCALIZED DOPANT DIFFUSION BARR...
- Publication number 20120187489
- Publication date Jul 26, 2012
- Commissariat A L'Energie Atomique et Aux Energies Alternatives
- Laurent GRENOUILLET
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FABRICATING A FIELD EFFECT DEVICE WITH WEAK JUNCTION CAP...
- Publication number 20120190214
- Publication date Jul 26, 2012
- Commissariat A L'Energie Atomique et Aux Energies Alternatives
- Maud VINET
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PROCESS FOR ASSEMBLING SUBSTRATES WITH LOW-TEMPERATURE HEAT TREATMENTS
- Publication number 20120088352
- Publication date Apr 12, 2012
- COMMISSARIAT A L'ENERGIE ATOMIQUE
- Rémi Beneyton
- C09 - DYES PAINTS POLISHES NATURAL RESINS ADHESIVES MISCELLANEOUS COMPOSITION...
Information Patent Application
METHOD FOR MAKING A SEMICONDUCTOR STRUCTURE WITH A BURIED GROUND PLANE
- Publication number 20110284870
- Publication date Nov 24, 2011
- COMMISS. A L'ENERGIE ATOM ET AUX ENERG ALTERNA
- Yannick Le Tiec
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PROCESS FOR ASSEMBLING SUBSTRATES WITH LOW-TEMPERATURE HEAT TREATMENTS
- Publication number 20090162991
- Publication date Jun 25, 2009
- COMMISSARIAT A L'ENERGIE ATOMIQUE
- Rémi Beneyton
- C09 - DYES PAINTS POLISHES NATURAL RESINS ADHESIVES MISCELLANEOUS COMPOSITION...

Yannick Le Tiec

Person

Patents Grantslast 30 patents

Method for manufacturing a fin MOS transistor

Low leakage dual STI integrated circuit including FDSOI transistors

Dual STI integrated circuit including FDSOI transistors and method...

Method for fabricating microelectronic devices with isolation trenc...

Defective P-N junction for backgated fully depleted silicon on insu...

Transistor with reduced parasitic capacitance and access resistance...

Dual channel hybrid semiconductor-on-insulator semiconductor devices

Method for manufacturing a fin MOS transistor

Method for treating the surface of a silicon substrate

Method for making a semiconductor structure with a buried ground plane

Contact isolation scheme for thin buried oxide substrate devices

Method to prepare semi-conductor device comprising a selective etch...

Method for producing a field effect transistor with implantation th...

Dual channel hybrid semiconductor-on-insulator semiconductor devices

Field effect transistor with offset counter-electrode contact

Microelectronic device with isolation trenches extending under an a...

Defective P-N junction for backgated fully depleted silicon on insu...

Method for producing a field effect transistor with a SiGe channel...

Method of producing insulation trenches in a semiconductor on insul...

Method for fabricating a field effect device with weak junction cap...

Process for assembling substrates with low-temperature heat treatments

Method for making a semiconductor structure with a buried ground plane

Patents Applicationslast 30 patents

METHOD FOR MANUFACTURING A FIN MOS TRANSISTOR

DUAL STI INTEGRATED CIRCUIT INCLUDING FDSOI TRANSISTORS AND METHOD...

LOW LEAKAGE DUAL STI INTEGRATED CIRCUIT INCLUDING FDSOI TRANSISTORS

METHOD FOR FABRICATING MICROELECTRONIC DEVICES WITH ISOLATION TRENC...

DUAL CHANNEL HYBRID SEMICONDUCTOR-ON-INSULATOR SEMICONDUCTOR DEVICES

DEFECTIVE P-N JUNCTION FOR BACKGATED FULLY DEPLETED SILICON ON INSU...

DUAL CHANNEL HYBRID SEMICONDUCTOR-ON-INSULATOR SEMICONDUCTOR DEVICES

DEFECTIVE P-N JUNCTION FOR BACKGATED FULLY DEPLETED SILICON ON INSU...

CONTACT ISOLATION SCHEME FOR THIN BURIED OXIDE SUBSTRATE DEVICES

METHOD FOR MANUFACTURING A FIN MOS TRANSISTOR

METHOD FOR PRODUCING A FIELD EFFECT TRANSISTOR WITH A SiGe CHANNEL...

METHOD FOR PRODUCING A FIELD EFFECT TRANSISTOR WITH IMPLANTATION TH...

MICROELECTRONIC DEVICE WITH ISOLATION TRENCHES EXTENDING UNDER AN A...

METHOD FOR MAKING A SEMICONDUCTOR STRUCTURE WITH A BURIED GROUND PLANE

METHOD FOR TREATING THE SURFACE OF A SILICON SUBSTRATE

METHOD OF PRODUCING INSULATION TRENCHES IN A SEMICONDUCTOR ON INSUL...

TRANSISTOR AND METHOD OF FABRICATION

METHOD TO PREPARE SEMI-CONDUCTOR DEVICE COMPRISING A SELECTIVE ETCH...

FIELD EFFECT TRANSISTOR WITH OFFSET COUNTER-ELECTRODE CONTACT

FIELD EFFECT DEVICE PROVIDED WITH A LOCALIZED DOPANT DIFFUSION BARR...

METHOD FOR FABRICATING A FIELD EFFECT DEVICE WITH WEAK JUNCTION CAP...

PROCESS FOR ASSEMBLING SUBSTRATES WITH LOW-TEMPERATURE HEAT TREATMENTS

METHOD FOR MAKING A SEMICONDUCTOR STRUCTURE WITH A BURIED GROUND PLANE

PROCESS FOR ASSEMBLING SUBSTRATES WITH LOW-TEMPERATURE HEAT TREATMENTS