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Yannick Marc NEVERS

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  • Sassenage, FR
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Patents Grantslast 30 patents

Patents Applicationslast 30 patents

  • Information Patent Application

    Multi-Stack Bitcell Architecture
    • Publication number 20240260261
    • Publication date Aug 1, 2024
    • ARM Limited
    • Yannick Marc Nevers
  • Information Patent Application

    Register Bank Architecture with Latches
    • Publication number 20240249790
    • Publication date Jul 25, 2024
    • ARM Limited
    • Yannis Jallamion-Grive
    • G11 - INFORMATION STORAGE
  • Information Patent Application

    Dynamic Memory Scrambling
    • Publication number 20170147509
    • Publication date May 25, 2017
    • ARM Limited
    • Yannick Marc NEVERS
    • G06 - COMPUTING CALCULATING COUNTING
  • Information Patent Application

    LOW POWER LATCHING CIRCUITS
    • Publication number 20140218089
    • Publication date Aug 7, 2014
    • ARM Limited
    • Virgile JAVERLIAC
    • G11 - INFORMATION STORAGE
  • Information Patent Application

    LOW POWER LATCHING CIRCUITS
    • Publication number 20140125392
    • Publication date May 8, 2014
    • ARM Limited
    • Virgile JAVERLIAC
    • G11 - INFORMATION STORAGE
  • Information Patent Application

    Generating ROM bit cell arrays
    • Publication number 20110249481
    • Publication date Oct 13, 2011
    • ARM Limited
    • Yannick Marc Nevers
    • G06 - COMPUTING CALCULATING COUNTING
  • Information Patent Application

    Read only memory cell for storing a multiple bit value
    • Publication number 20110051487
    • Publication date Mar 3, 2011
    • ARM Limited
    • Yannick Marc Nevers
    • G11 - INFORMATION STORAGE
  • Information Patent Application

    Generating ROM bit cell arrays
    • Publication number 20100177544
    • Publication date Jul 15, 2010
    • ARM Limited
    • Yannick Marc Nevers
    • G06 - COMPUTING CALCULATING COUNTING