Yanran Chen

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San Jose, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
Designing single event upset latches
- Patent number 11,652,481
- Issue date May 16, 2023
- Xilinx, Inc.
- Pierre Maillard
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
On-die virtual probes (ODVP) for integrated circuitries
- Patent number 11,428,733
- Issue date Aug 30, 2022
- Xilinx, Inc.
- Yanran Chen
- G01 - MEASURING TESTING
Information Patent Grant
Single event latch-up (SEL) mitigation detect and mitigation
- Patent number 10,958,067
- Issue date Mar 23, 2021
- Xilinx, Inc.
- Pierre Maillard
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Circuit for and method of storing data in an integrated circuit device
- Patent number 10,574,214
- Issue date Feb 25, 2020
- Xilinx, Inc.
- Pierre Maillard
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Circuit for and method of storing data in an integrated circuit device
- Patent number 10,263,623
- Issue date Apr 16, 2019
- Xilinx Inc.
- Yanran Chen
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
INTEGRATED CIRCUIT TRANSACTION REDUNDANCY
- Publication number 20240111693
- Publication date Apr 4, 2024
- Xilinx, Inc.
- Krishnan SRINIVASAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FLEXIBLE QUEUE PROVISIONING FOR PARTITIONED ACCELERATION DEVICE
- Publication number 20230290189
- Publication date Sep 14, 2023
- Xilinx, Inc.
- Yanran CHEN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DESIGNING SINGLE EVENT UPSET LATCHES
- Publication number 20230055458
- Publication date Feb 23, 2023
- Xilinx, Inc.
- Pierre MAILLARD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SINGLE EVENT LATCH-UP (SEL) MITIGATION DETECT AND MITIGATION
- Publication number 20200091713
- Publication date Mar 19, 2020
- Xilinx, Inc.
- Pierre Maillard
- H03 - BASIC ELECTRONIC CIRCUITRY