Yasunobu Kai

Person

Kanagawa-ken, JP

People

Patents Grantslast 30 patents

Information Patent Grant
Surface emitting quantum cascade laser
- Patent number 10,630,059
- Issue date Apr 21, 2020
- Kabushiki Kaisha Toshiba
- Shinji Saito
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Substrate including photonic crystal and method for manufacturing t...
- Patent number 10,490,979
- Issue date Nov 26, 2019
- Kabushiki Kaisha Toshiba
- Rei Hashimoto
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Surface emitting quantum cascade laser
- Patent number 10,424,899
- Issue date Sep 24, 2019
- Kabushiki Kaisha Toshiba
- Shinji Saito
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit device, method for producing mask layout, and pr...
- Patent number 9,257,367
- Issue date Feb 9, 2016
- Kabushiki Kaisha Toshiba
- Motohiro Okada
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Production method and evaluation apparatus for mask layout
- Patent number 9,086,634
- Issue date Jul 21, 2015
- KABUSHIKI KAISHA TOSHIBA
- Yuko Kono
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Exposure tolerance estimation method and method for manufacturing s...
- Patent number 8,956,791
- Issue date Feb 17, 2015
- Kabushiki Kaisha Toshiba
- Osamu Yamane
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Semiconductor device and manufacturing method of semiconductor device
- Patent number 8,865,589
- Issue date Oct 21, 2014
- Kabushiki Kaisha Toshiba
- Takaki Hashimoto
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Semiconductor device manufacturing method
- Patent number 8,679,731
- Issue date Mar 25, 2014
- Kabushiki Kaisha Toshiba
- Kazuya Fukuhara
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Photomask designing method and photomask designing program
- Patent number 8,423,922
- Issue date Apr 16, 2013
- Kabushiki Kaisha Toshiba
- Yasunobu Kai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for determining position of auxiliary pattern, method for ma...
- Patent number 8,336,000
- Issue date Dec 18, 2012
- Kabushiki Kaisha Toshiba
- Yasunobu Kai
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Semiconductor device manufacturing method
- Patent number 8,293,456
- Issue date Oct 23, 2012
- Kabushiki Kaisha Toshiba
- Kazuya Fukuhara
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Semiconductor device and method of manufacturing the same
- Patent number 8,288,812
- Issue date Oct 16, 2012
- Kabushiki Kaisha Toshiba
- Yasunobu Kai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Pattern layout of integrated circuit
- Patent number 7,941,782
- Issue date May 10, 2011
- Kabushiki Kaisha Toshiba
- Yasunobu Kai
- G11 - INFORMATION STORAGE
Information Patent Grant
Parameter adjustment method, semiconductor device manufacturing met...
- Patent number 7,934,175
- Issue date Apr 26, 2011
- Kabushiki Kaisha Toshiba
- Toshiya Kotani
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Pattern layout for forming integrated circuit
- Patent number 7,682,757
- Issue date Mar 23, 2010
- Kabushiki Kaisha Toshiba
- Hiromitsu Mashita
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY

Patents Applicationslast 30 patents

Information Patent Application
SURFACE EMITTING QUANTUM CASCADE LASER
- Publication number 20200006922
- Publication date Jan 2, 2020
- KABUSHIKI KAISHA TOSHIBA
- Shinji SAITO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SUBSTRATE INCLUDING PHOTONIC CRYSTAL AND METHOD FOR MANUFACTURING T...
- Publication number 20190199064
- Publication date Jun 27, 2019
- KABUSHIKI KAISHA TOSHIBA
- Rei HASHIMOTO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SURFACE EMITTING QUANTUM CASCADE LASER
- Publication number 20190074663
- Publication date Mar 7, 2019
- KABUSHIKI KAISHA TOSHIBA
- Shinji SAITO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE AND DESIGN APPARATUS FOR SEMICONDUCTOR DEVICE
- Publication number 20150263026
- Publication date Sep 17, 2015
- KABUSHIKI KAISHA TOSHIBA
- Yuko KONO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
- Publication number 20150008584
- Publication date Jan 8, 2015
- Kabushiki Kaisha Toshiba
- Takaki Hashimoto
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
EXPOSURE TOLERANCE ESTIMATION METHOD AND METHOD FOR MANUFACTURING S...
- Publication number 20140287350
- Publication date Sep 25, 2014
- KABUSHIKI KAISHA TOSHIBA
- Osamu YAMANE
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
INTEGRATED CIRCUIT DEVICE, METHOD FOR PRODUCING MASK LAYOUT, AND PR...
- Publication number 20140252639
- Publication date Sep 11, 2014
- KABUSHIKI KAISHA TOSHIBA
- Motohiro OKADA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PRODUCTION METHOD AND EVALUATION APPARATUS FOR MASK LAYOUT
- Publication number 20140242498
- Publication date Aug 28, 2014
- KABUSHIKI KAISHA TOSHIBA
- Yuko Kono
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
- Publication number 20130241073
- Publication date Sep 19, 2013
- Takaki Hashimoto
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE MANUFACTURING METHOD
- Publication number 20120328992
- Publication date Dec 27, 2012
- Kabushiki Kaisha Toshiba
- Kazuya Fukuhara
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
EXPOSURE METHOD AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
- Publication number 20120070985
- Publication date Mar 22, 2012
- Takaki Hashimoto
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
Method for Determining Position of Auxiliary Pattern, Method for Ma...
- Publication number 20120064732
- Publication date Mar 15, 2012
- Yasunobu Kai
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
PHOTOMASK DESIGNING METHOD AND PHOTOMASK DESIGNING PROGRAM
- Publication number 20110072402
- Publication date Mar 24, 2011
- Kabushiki Kaisha Toshiba
- Yasunobu KAI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
- Publication number 20110049601
- Publication date Mar 3, 2011
- Yasunobu Kai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PATTERN FORMING METHOD
- Publication number 20100304568
- Publication date Dec 2, 2010
- Seiro MIYOSHI
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
SEMICONDUCTOR MEMORY DEVICE
- Publication number 20100202181
- Publication date Aug 12, 2010
- Takaki HASHIMOTO
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR DEVICE MANUFACTURING METHOD
- Publication number 20090220894
- Publication date Sep 3, 2009
- Kazuya FUKUHARA
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
- Publication number 20090142706
- Publication date Jun 4, 2009
- Kazuyuki Masukawa
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
PARAMETER ADJUSTMENT METHOD, SEMICONDUCTOR DEVICE MANUFACTURING MET...
- Publication number 20080250381
- Publication date Oct 9, 2008
- Toshiya KOTANI
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
PATTERN LAYOUT OF INTEGRATED CIRCUIT
- Publication number 20080137421
- Publication date Jun 12, 2008
- Yasunobu KAI
- G11 - INFORMATION STORAGE
Information Patent Application
Pattern layout for forming integrated circuit
- Publication number 20060228636
- Publication date Oct 12, 2006
- Hiromitsu Mashita
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY

Yasunobu Kai

Person

Patents Grantslast 30 patents

Surface emitting quantum cascade laser

Substrate including photonic crystal and method for manufacturing t...

Surface emitting quantum cascade laser

Integrated circuit device, method for producing mask layout, and pr...

Production method and evaluation apparatus for mask layout

Exposure tolerance estimation method and method for manufacturing s...

Semiconductor device and manufacturing method of semiconductor device

Semiconductor device manufacturing method

Photomask designing method and photomask designing program

Method for determining position of auxiliary pattern, method for ma...

Semiconductor device manufacturing method

Semiconductor device and method of manufacturing the same

Pattern layout of integrated circuit

Parameter adjustment method, semiconductor device manufacturing met...

Pattern layout for forming integrated circuit

Patents Applicationslast 30 patents

SURFACE EMITTING QUANTUM CASCADE LASER

SUBSTRATE INCLUDING PHOTONIC CRYSTAL AND METHOD FOR MANUFACTURING T...

SURFACE EMITTING QUANTUM CASCADE LASER

SEMICONDUCTOR DEVICE AND DESIGN APPARATUS FOR SEMICONDUCTOR DEVICE

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

EXPOSURE TOLERANCE ESTIMATION METHOD AND METHOD FOR MANUFACTURING S...

INTEGRATED CIRCUIT DEVICE, METHOD FOR PRODUCING MASK LAYOUT, AND PR...

PRODUCTION METHOD AND EVALUATION APPARATUS FOR MASK LAYOUT

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

SEMICONDUCTOR DEVICE MANUFACTURING METHOD

EXPOSURE METHOD AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Method for Determining Position of Auxiliary Pattern, Method for Ma...

PHOTOMASK DESIGNING METHOD AND PHOTOMASK DESIGNING PROGRAM

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

PATTERN FORMING METHOD

SEMICONDUCTOR MEMORY DEVICE

SEMICONDUCTOR DEVICE MANUFACTURING METHOD

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

PARAMETER ADJUSTMENT METHOD, SEMICONDUCTOR DEVICE MANUFACTURING MET...

PATTERN LAYOUT OF INTEGRATED CIRCUIT

Pattern layout for forming integrated circuit