Yau-Tsun Steven Li

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San Jose, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
Adaptive compilation and execution for hardware acceleration
- Patent number 10,216,217
- Issue date Feb 26, 2019
- Xilinx, Inc.
- Sonal Santan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Delay modeling for high fan-out nets within circuit designs
- Patent number 10,108,769
- Issue date Oct 23, 2018
- Xilinx, Inc.
- Yau-Tsun S. Li
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Re-budgeting connections of a circuit design
- Patent number 8,972,920
- Issue date Mar 3, 2015
- Xilinx, Inc.
- Grigor S. Gasparyan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Replicating a driver of a net in a circuit design
- Patent number 8,769,461
- Issue date Jul 1, 2014
- Xilinx, Inc.
- Yau-Tsun S. Li
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Timing analysis of a mapped logic design using physical delays
- Patent number 7,886,256
- Issue date Feb 8, 2011
- Xilinx, Inc.
- Pradip Kumar Jha
- G06 - COMPUTING CALCULATING COUNTING